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Signal processing at 250 MHz using high-performance FPGA's

B. Von Herzen
1998 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Experimental results indicate that CMOS FPGA's can perform useful computation at 250 MHz.  ...  This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy.  ...  Jon Brunetti completed the high-speed board design and board layout for the 250 MHz FPGA correlator test fixture.  ... 
doi:10.1109/92.678878 fatcat:gmsrt3t6grasxiv2st4bukhgf4

Signal processing at 250 MHz using high-performance FPGA's

Brian Von Herzen
1997 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97  
Intel's Pentium, often today's standard of high-frequency operation, was only running at 75-100MHz in 0.5m and 0.6m technologies. You wouldn't even see a 200MHz Pentium until 0.35 micron.  ...  Von Herzen shows that he can extract useful 250MHz operation out of a 0.6m (today we might say 600nm) Xilinx XC3100A in 1997many FPGA users would be happy to see that performance today out of their 45nm  ...  Intel's Pentium, often today's standard of high-frequency operation, was only running at 75-100MHz in 0.5m and 0.6m technologies. You wouldn't even see a 200MHz Pentium until 0.35 micron.  ... 
doi:10.1145/258305.258313 dblp:conf/fpga/Herzen97 fatcat:yilvzchdhfedfkh2lh4lbpgy6q

Electronics development for the ATLAS liquid argon calorimeter trigger and readout for future LHC running

Walter Hopkins
2017 Nuclear Instruments and Methods in Physics Research Section A : Accelerators, Spectrometers, Detectors and Associated Equipment  
up to 312 super cell signals • Pre-prototype (ABBA) installed in summer 2014 st level trigger at 1 MHz shall use LAr Supercell information as input • 2 nd level trigger at 400 kHz exploits full LAr Calorimeter  ...  redundant signal paths being studied • Multiple ADC's used, if DoutA is to high (compatible with an SEE) use output from DoutB Feb. 5, 2015 11 SEE -Split-ADC Redunda A B in SEE Detector  ... 
doi:10.1016/j.nima.2016.04.037 fatcat:2vojm22i75dclkrc37eaxvhkay

Terabit optical local area networks for multiprocessing systems

Ted H. Szymanski, Albert Au, Myriam Lafrenière-Roula, Victor Tyan, Boonchuay Supmonchai, James Wong, Belkacem Zerrouk, Stefan Thomas Obenaus
1998 Applied Optics  
When the Motorola Optobus fiber technology is used, each workstation has a data bandwidth of 6.4 Gbits͞s to the core.  ...  One is used for the bit clock, i.e., the 800-MHz clock used by the clock-divider module. The second bit is the frame signal used to denote the start of a packet frame.  ...  The simplified core can be scaled upward to 32 I͞O ports and pipelined to operate the internal data paths at 400 MHz or higher without exceeding the density of the CMOS process.  ... 
doi:10.1364/ao.37.000264 pmid:18268582 fatcat:avohkkfsd5gvboowfb6fcmqbcq

TIME-INTERLEAVED DELTA-SIGMA MODULATOR FOR WIDEBAND DIGITAL GHZ TRANSMITTERS DESIGN AND SDR APPLICATIONS

Mohammad Mojtaba Ebrahimi, Mohamed Helaoui, Fadhel M. Ghannouchi
2011 Progress in Electromagnetics Research B  
In this paper, the bandwidth of the fully digital transmitter is increased 8 times using parallel processing time-interleaved architecture, while maintaining the same signal quality.  ...  The concept was assessed in terms of SNDR by using a differential logic analyzer at the output of FPGA, and the SNDR was found to be around 60 dB.  ...  Using differential signals reduces the noise and parasitics, which is very useful at these high-speed frequencies.  ... 
doi:10.2528/pierb11071205 fatcat:n6ybjffwcbgmnatrcauyx5cu7y

DSPs/FPGAs Comparative Study for Power Consumption, Noise Cancellation, and Real Time High Speed Applications

Alon Hayim, Michael Knieser, Maher Rizkalla
2010 Journal of Software Engineering and Applications  
FPGAs can handle more processes at the same time when compared to DSPs, while the later can only handle a limited number of parallel instructions at a time.  ...  Both DSP processors and FPGAs were studied with respect to their performance in power consumption, hardware architecture, and speed for real time applications.  ...  In high performance signal processing applications, FPGAs have several advantages over high end DSP processors.  ... 
doi:10.4236/jsea.2010.34044 fatcat:2steo4f5pvbzbcfeqnk5ia5nuu

The ALMA correlator

R. P. Escoffier, G. Comoretto, J. C. Webber, A. Baudry, C. M. Broadwell, J. H. Greenberg, R. R. Treacy, P. Cais, B. Quertier, P. Camino, A. Bos, A. W. Gunst
2006 Astronomy and Astrophysics  
The Atacama Large Millimeter Array (ALMA) is an international astronomy facility to be used for detecting and imaging all types of astronomical sources at millimeter and submillimeter wavelengths at a  ...  The main digital signal processing features and a block diagram of the correlator being constructed for the ALMA radio astronomy observatory are presented.  ...  for Astronomical Research in the Southern Observatory (ESO), in Japan by the National Institutes of Natural Sciences (NINS) in cooperation with the Academia Sinica in Taiwan and in North America by the US  ... 
doi:10.1051/0004-6361:20054519 fatcat:l5kou4o4onatjdg7hxvchpmdbu

The power of communication: Energy-efficient NOCS for FPGAS

Mohamed S. Abdelfattah, Vaughn Betz
2013 2013 23rd International Conference on Field programmable Logic and Applications  
For complete systems, hard NoCs consume less than 6% (and as low as 3%) of the FPGA's dynamic power budget to support 100 GB/s of communication bandwidth.  ...  can improve device scalability and facilitate design by abstracting communication and simplifying timing closure, not only between modules in the FPGA fabric but also with large "hard" blocks such as high-speed  ...  Under high traffic, this NoC consumes 5.1 W of power or approximately one third of the FPGA's power budget.  ... 
doi:10.1109/fpl.2013.6645496 dblp:conf/fpl/AbdelfattahB13 fatcat:qbieo75nqrbtjms5zy76yuoo5u

SiGe HBT BiCMOS FPGAs for fast reconfigurable computing

B.S. Goda, J.F. McDonald, S.R. Carlough, T.W. Krawczyk, R.P. Kraft
2000 IEE Proceedings - Computers and digital Techniques  
To reduce power dissipation, the con®guration bits used to de®ne the FPGA's function will be stored in CMOS memory.  ...  The paper proposes a high speed SiGe heterojunction bipolar transistor (HBT) FPGA design co-integrated with CMOS in an IBM BiCMOS process.  ...  However, the relatively slow operating speeds of current FPGAs (30±70 MHz), prevents their use in high speed digital systems.  ... 
doi:10.1049/ip-cdt:20000468 fatcat:7m5z2xghuzgyfgiv2xfsgvsz3q

Reconfigurable framework for high-bandwidth stream-oriented data processing

Alexander Mykyta, Dorin Patru, Eli Saber, Gene Roylance, Brad Larson
2012 2012 IEEE International SOC Conference  
The modern FPGA's ability to be partially reconfigured at runtime allows for the device to have the flexibility normally associated with a processor, while also being able to implement digital logic like  ...  Performance of the system is evaluated by comparing its computational throughput to previous efforts using the CSC engine as well as the performance gained from the flexible scheduling that the framework  ...  of 8-bytes at every 250 MHz clock edge.  ... 
doi:10.1109/socc.2012.6398391 dblp:conf/socc/MykytaPSRL12 fatcat:yasut6izkzbhzmjiu57tcjnxpa

Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses

Mohamed S. Abdelfattah, Vaughn Betz
2016 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
When comparing a hard NoC against soft buses that are currently used for interconnection, we find that a typical system is 4× smaller, and uses 23% less energy when implemented using the hard NoC even  ...  For complete systems, hard NoCs consume <6% (and as low as 3%) of the FPGA's dynamic power budget to support 100 GB/s of communication bandwidth.  ...  MHz, while no pipeline stages were necessary in connecting a single module to the PCIe interface at 250 MHz.  ... 
doi:10.1109/tvlsi.2015.2397005 fatcat:efzplnl73nhltjjp6l7vszfpgm

A phase assignment method for virtual-wire-based hardware emulation

Hsiao-Pin Su, Youn-Long Lin
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
For TDM to be effective, each transportation of an inter-FPGA signal must be carefully assigned to a slot of the time division.  ...  In a hardware emulator consisting of multiple fieldprogrammable gate arrays (FPGA's), the utilization of the FPGA logic resource is usually very low due to the limitation on the number of I/O pins.  ...  We use Fig. 2 to illustrate the operation principle of virtual wiring. Suppose the emulator is to run at 1 MHz, and the longest combinational path travels across six FPGA's.  ... 
doi:10.1109/43.644040 fatcat:t47gkr4bkfhd7eint4o6yugoui

Design of a Low Latency and High Throughput Packet Classification Module on FPGA Platform

2020 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
So there is the demand for high-speed packet classifiers to reduce the network complexity and improve the network performance.  ...  If the size of the network is vast and complexity will arise to perform the different operations, which affects the network performance and other constraints also.  ...  The Decision Tree PC works at 100 MHz using Spartan -3E FPGA Board.  ... 
doi:10.35940/ijitee.f4195.049620 fatcat:yw5q4k4d6vd5boju5kwtialw6m

The ALMA 64-antenna correlator: Main technical features and science modes

Alain Baudry, John Webber
2011 2011 XXXth URSI General Assembly and Scientific Symposium  
All correlator parts have been constructed, 3 quadrants are delivered to the 5000-m high site and 2 have been commissioned for ALMA Early Science.  ...  as well as at 5000 m in Chile.  ...  Correlator IPT acknowledges continuous support from NRAO and ESO at Charlottesville and University of Bordeaux, respectively.  ... 
doi:10.1109/ursigass.2011.6051253 fatcat:craew6ayb5drvkmd6swumus25q

Multi-Channel Data Acquisition Card under New Acquisition and Transmission Architecture of High Frequency Ground Wave Radar

Yang Bai, Xin Zhang, Qiang Yang, Yong Yang, Weibo Deng, Di Yao
2021 Sensors  
In order to meet the requirements of real-time processing and accurate transmission of echo signals in high-frequency ground-wave radar (HFGWR) systems, a new acquisition and transmission framework utilizing  ...  It is known that the data acquisition and processing system plays an important role in radar target detection system.  ...  Parameters Value Input Signal Frequency (MHz) 75.01 Input Signal Amplitude (mV) 500 Sampling rate (MHz) 250 Acquisition mode DDC Bandwidth (KHz) 50 Output sample rate (KHz) 400 Trigger  ... 
doi:10.3390/s21041128 pmid:33562798 fatcat:bw6tf7gaujclxcr35cptoefo2u
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