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Side-Channel Leakage of Masked CMOS Gates [chapter]

Stefan Mangard, Thomas Popp, Berndt M. Gammel
2005 Lecture Notes in Computer Science  
Glitches occur in every CMOS circuit. Consequently, the currently known masking schemes for CMOS gates do not prevent DPA attacks.  ...  There are many articles and patents on the masking of logic gates. However, the existing publications assume that a masked logic gate switches its output no more than once per clock cycle.  ...  equal and hence, there is a leakage of side-channel information.  ... 
doi:10.1007/978-3-540-30574-3_24 fatcat:eviduuqngvfppkfrauzpqguezi

Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations [chapter]

Stefan Mangard, Kai Schramm
2006 Lecture Notes in Computer Science  
We subsequently show that the side-channel leakage of the masked multipliers can be prevented by fulfilling timing constraints for 3 · n XOR gates in each GF (2 n ) multiplier of an AES S-box.  ...  Motivated by this fact, we pinpointed which parts of masked AES S-boxes cause the glitches that lead to side-channel leakage.  ...  It is important to point out that it is exclusively this effect that accounts for the side-channel leakage of the masked AND gate.  ... 
doi:10.1007/11894063_7 fatcat:qzakzmwjfzbwvmlpscu5vgznii

A 10k-Cycling Reliable 90nm Logic NVM "eCFlash" (Embedded CMOS Flash) Technology

S. Shukuri, S. Shimizu, N. Ajika, T. Ogura, M. Mihara, Y. Kawajiri, K. Kobayashi, M. Nakashima
2011 2011 3rd IEEE International Memory Workshop (IMW)  
In the eCFlash element, the charge is stored in the side spacer region of CMOS transistor, consequently its charge loss process is not influenced by the leakage current through the gate oxide and surface  ...  leakage current on the side spacer, which is the most serious charge loss issues of the conventional single poly type floating gate NVM.  ...  eCFlash Element and Operation N-channel eCFlash single NVM elements have been fabricated in a 90nm CMOS process without any mask adder and any process change.  ... 
doi:10.1109/imw.2011.5873184 fatcat:vysyp5h4gnbdrdabv375gqofhe

Diffusion-rounded CMOS for improving both Ion and Ioff characteristics

Myunghwan Ryu, Hung Viet Nguyen, Youngmin Kim
2011 IEICE Electronics Express  
The proposed diffusion-rounded CMOS shows as much as 10% improvement in the on-current (driving) and the off-current (leakage) is saved up to 10%.  ...  TCAD analysis shows that diffusion rounding at the transistor source side can provide increased I on with decreased I off because of the edge effect.  ...  Acknowledgments This work was supported by the 2009 Research Fund of the UNIST (Ulsan National Institute of Science and Technology). This work also was partially sponsored by NRF grant #2010-0012867.  ... 
doi:10.1587/elex.8.1783 fatcat:i3gfrnnufbeslfvxcua34ctluq

Power analysis of the t-private logic style for FPGAs

Zachary N. Goddard, Nicholas LaJeunesse, Thomas Eisenbarth
2015 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)  
channel leakage.  ...  It has been found that masking can be overcome by higher order side channel analysis.  ...  It has been found that masking can be overcome by higher order side channel analysis.  ... 
doi:10.1109/hst.2015.7140239 dblp:conf/host/GoddardLE15 fatcat:xplobplzxje4zbek7l3ezs3udi

Effect of glitches against masked AES S-box implementation and countermeasure

M. Alam, D. Mukhopadhyay, S. Ghosh, I.S. Gupta, D.R. Chowdhury, M.J. Mohan
2009 IET Information Security  
The phenomenon in CMOS circuits responsible for the leakage of masked circuits is known as glitching.  ...  It has been shown that the logic circuits used in the implementation of cryptographic algorithms leak side-channel information inspite of masking, which can be exploited, in differential power attacks.  ...  [16] , reported that all proposed masked gates are vulnerable to powerbased side-channel leakage in the presence of glitches.  ... 
doi:10.1049/iet-ifs:20080041 fatcat:whlkfmb65jdtdoiwnjhhgxgt4e

Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments

Thorben Moos
2019 Transactions on Cryptographic Hardware and Embedded Systems  
Previous articles have shown that this source of energy dissipation, at least in case of digital CMOS logic, can successfully be exploited as a side-channel to recover the secrets of cryptographic implementations  ...  static leakage measurements affects the security provided by masked implementations.  ...  supported in part by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Germany's Excellence Strategy -EXC 2092 CASA -390781972 and through the project 271752544 "NaSCA: Nano-Scale Side-Channel  ... 
doi:10.13154/tches.v2019.i3.202-232 dblp:journals/tches/Moos19 fatcat:6uc5qvusonhx3gubdetpdbi2xm

A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques [chapter]

Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh
2009 Lecture Notes in Computer Science  
This is the first result demonstrating reduction of the side-channel leakage by glitch suppression quantitatively on real ASIC.  ...  The original RSL proposed in 2004 requires a unique RSL-gate for random data masking and glitch suppression to prevent secret information leakage through power traces.  ...  Acknowledgments SASEBO boards were developed by AIST and Tohoku University in undertaking projects sponsored by METI (Ministry of Economy, Trade and Industry, Japan).  ... 
doi:10.1007/978-3-642-04138-9_14 fatcat:vgolhgokdja4xg7tc5jll5vppy

Masking at Gate Level in the Presence of Glitches [chapter]

Wieland Fischer, Berndt M. Gammel
2005 Lecture Notes in Computer Science  
In this paper, we refine the model for the power consumption of CMOS gates taking into account the side-channel of glitches.  ...  It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by "secure" random masking schemes, leak side-channel information, which can be exploited  ...  In the next section a model for the power consumption of CMOS gates is developed which takes into account the side-channel of glitches.  ... 
doi:10.1007/11545262_14 fatcat:hbv32qumpvb4zizhkpcpg6ggg4

C-V test structures for metal gate CMOS

R.G. Bankras, M.P.J. Tiggelman, M. Adi Negara, G.T. Sasse, J. Schmitz
2006 2006 IEEE International Conference on Microelectronic Test Structures  
Gate leakage has complicated the layout and measurement of C-V test structures. In this paper the impact of metal gate introduction to C-V test structure design is discussed.  ...  The metal gate allows for widergate structures and for the application of n + -p + diffusion edges.  ...  ACKNOWLEDGEMENTS We wish to thank Tom Aarnink for technical support with the ALD processing, and Henk de Vries of the department of IC Design for his assistance with the RF measurements.  ... 
doi:10.1109/icmts.2006.1614309 fatcat:irfpq6gdwbf5pecgooworkkyzy

Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal

Bijan Fadaeinia, Thorben Moos, Amir Moradi
2021 Applied Sciences  
The imbalance of the currents leaked by CMOS standard cells when different logic values are applied to their inputs can be exploited as a side channel to recover the secrets of cryptographic implementations  ...  Traditional side-channel countermeasures, primarily designed to thwart the dynamic leakage behavior, were shown to be much less powerful against this static threat.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/app11157143 fatcat:fgm2r5l3hbgfbiu57s4cl2ae6q

Overview and status of metal S/D Schottky-barrier MOSFET technology

J.M. Larson, J.P. Snyder
2006 IEEE Transactions on Electron Devices  
enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar  ...  These and other benefits accrue using a lowthermal-budget CMOS manufacturing process requiring two fewer masks than conventional bulk CMOS.  ...  This dual-silicide exclusion-mask process requires only two masks compared to four for a typical doped S/D CMOS process. There are significant process advantages with SB-CMOS technology.  ... 
doi:10.1109/ted.2006.871842 fatcat:tchstxgkcvesxckahotk7nqnci

Countermeasures against Static Power Attacks

Thorben Moos, Amir Moradi
2021 Transactions on Cryptographic Hardware and Embedded Systems  
Thus, for adversaries who seek to extract secrets from cryptographic devices via side-channel analysis, the static power has become an attractive quantity to obtain.  ...  Most works have focused on the destructive side of this subject by demonstrating attacks.  ...  supported in part by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Germany's Excellence Strategy -EXC 2092 CASA -390781972 and through the project 271752544 "NaSCA: Nano-Scale Side-Channel  ... 
doi:10.46586/tches.v2021.i3.780-805 fatcat:ijtafumtffghhinhss5oarvdia

Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage [chapter]

Zhimin Chen, Yujie Zhou
2006 Lecture Notes in Computer Science  
Based on our model, we demonstrate that 1-bit masked logic gates with asynchronous inputs always leak side-channel information from their output transitions.  ...  Recent research has shown that cryptographers with glitches are vulnerable in front of Side Channel Attacks (SCA).  ...  Since AND and OR gates are the main components of cryptographers, so we can say that delay of the mask signal also has side channel leakage.  ... 
doi:10.1007/11894063_20 fatcat:q4gx74lrcnhjdnzqyvwnhjsnuq

CMOS 1 MICRON ISOLATION TECHNOLOGY USING INTERFACE SEALING BY PLASMA NITRIDATION : PLASMA SILO

P. DELPECH, B. VUILLERMOZ, M. BERENGUER, A. STRABONI, T. TERNISIEN
1988 Le Journal de Physique Colloques  
The PLASMA SILO provides a reduction of 0.4 pm in the channel width loss, and a gain on the narrow channel effect.  ...  The other electrical characteristics are maintained (subthreshold characteristics, gate oxide integrity, etc, )  ...  ACKNOWLEDGEMENTS We would like to thank the technical staff of the pilot line for the processing of the wafers, and D.T.Amm and M.Haond for their critical review of the manuscript.  ... 
doi:10.1051/jphyscol:19884110 fatcat:44mezhxgnve2hkvrz2355whm5i
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