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SiGe digital frequency dividers with reduced residual phase noise

Stephen Horst, Stan Phillips, Hossein Lavasani, Farrokh Ayazi, John D. Cressler
2009 2009 IEEE Custom Integrated Circuits Conference  
A new design methodology for achieving very low residual phase noise in SiGe HBT digital frequency dividers is presented.  ...  A modified CML D latch design is proposed that enables the latch to draw more current, thereby reducing the residual phase noise.  ...  Several theoretical analyses of residual phase noise in digital frequency dividers have been presented, most recently by Levantino et al. [4] , [5] .  ... 
doi:10.1109/cicc.2009.5280851 dblp:conf/cicc/HorstPLAC09 fatcat:ethljdjdx5ewfkzpjkokgxtpae

Digital-IF WCDMA handset transmitter IC in 0.25-/spl mu/m SiGe BiCMOS

V.W. Leung, L.E. Larson, P.S. Gudem
2004 IEEE Journal of Solid-State Circuits  
Index Terms-Digital-IF, digital-to-analog converter (DAC), heterodyne, high-order hold, mixer, RF amplifier, SiGe, singlesideband (SSB), transmitter, wideband code division multiple access (WCDMA).  ...  Based on a digital-IF heterodyne architecture, it eliminates the external IF surface acoustic wave filter by adopting a meticulous frequency plan and a special-purpose second-order-hold D/A conversion  ...  ACKNOWLEDGMENT The authors would like to thank Semiconductor Research Corporation (SRC) and the sponsoring companies of the "SRC SiGe Design Challenge" for the IC chip fabrication. They also  ... 
doi:10.1109/jssc.2004.836337 fatcat:h5njdifrrvhujlwoyjabfamhmm

Integrated circuit technology options for RFICs-present status and future directions

L.E. Larson
1998 IEEE Journal of Solid-State Circuits  
Radio transceiver circuits have a very broad range of requirements-including noise figure, linearity, gain, phase noise, and power dissipation.  ...  This paper will summarize the technology tradeoffs that are involved in the implementation of radio frequency integrated circuits for wireless communications.  ...  Reported frequency divider residual phase noise normalized to 10 GHz [50] .  ... 
doi:10.1109/4.661204 fatcat:rls7ep3plzfinjlkzascigsoli

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

Jean-Guy Tartarin, Éric Tournier, Christophe Viallon
2022 Electronics  
The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints.  ...  The core of the article is oriented toward the noise of synthesized signals and frequency conversion.  ...  filter, frequency divider on the same die with the mixer) stands as an attractive solution in terms of performance/cost as far as VCOs offer state-of-the-art phase noise performances.  ... 
doi:10.3390/electronics11050684 fatcat:ylswmn2u6vdopcycocyr2fnkvu

Techniques for in-band phase noise reduction in ΔΣ synthesizers

T.A.D. Riley, N.M. Filiol, Qinghong Du, J. Kostamovaara
2003 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
This paper reviews several techniques used to reduce the in-band phase noise contribution of 16 fractional-N frequency synthesizers.  ...  As an example, it presents a synthesizer with an in-band phase noise floor of 97 dBc/Hz@10 KHz for an RF output frequency of 2.432 GHz and a reference frequency of 16 MHz.  ...  More importantly, for reducing in-band phase noise, it reduces the active range of the jitter coming out of the divider.  ... 
doi:10.1109/tcsii.2003.819132 fatcat:jfddeeu4rvhvxiw76dpkn5ajrq

W-Band Silicon-Based Frequency Synthesizers Using Injection-Locked and Harmonic Triplers

Chun-Cheng Wang, Zhiming Chen, Payam Heydari
2012 IEEE transactions on microwave theory and techniques  
Two monolithically integrated W-band frequency synthesizers are presented. Implemented in a 0.18 m SiGe BiCMOS with of 200/180 GHz, both circuits incorporate the same 30.3-33.8 GHz PLL core.  ...  The measured RMS phase noise for ILFT-and HBFT-based synthesizers are 5.4 and 5.5 (100 kHz to 100 MHz integration), while phase noise at 1 MHz offset is and dBc/Hz, respectively, at 96 GHz from a reference  ...  These phase noise measurements verify that in a synthesizer incorporating a low phase noise subharmonic PLL followed by an ILFT or an HBFT, the residual increase in phase noise is less than a typical  ... 
doi:10.1109/tmtt.2011.2180399 fatcat:7zfjtnocvzh3bic4ewxhesq4ia

Digital signal processing - up to microwave frequencies

P. Asbeck, I. Galton, Keh-Chung Wang, J.F. Jensen, A.K. Oki, C.T.M. Chang
2002 IEEE transactions on microwave theory and techniques  
Clock frequencies already exceed 1 GHz in some Si CMOS-based consumer products, and even higher speeds are attainable in specialized technologies, such as those based on GaAs, InP, and SiGe bipolar and  ...  Critical interfaces between the digital and analog domains are provided by analog-to-digital converters, digital-to-analog converters, and fractional-frequency synthesizers.  ...  Phase-locked loops synthesizing frequencies up to 40 GHz have been demonstrated with digital dividers; dynamic dividers can be used in this application, to achieve higher speed or save power.  ... 
doi:10.1109/22.989973 fatcat:twp474hatzbdfnlcf77znnao7u

RFIC 2020 Program

2020 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
Combined with frequency dithering scheme, the proposed method reduces EMI noise by 36.9dB and 49.1dB at 10MHz and 100MHz respectively.  ...  a divide-by-4 TSPC frequency divider operating with supply voltages from 0.4 V to 0.9 V and covering input frequency ranges from below 100 MHz to 70 GHz and beyond.  ...  The design is verified with digitally-modulated signals with a bandwidth of up to 160 MHz at a carrier frequency of 2 GHz.  ... 
doi:10.1109/rfic49505.2020.9218389 fatcat:fqkpw3oau5gzpoi3gscgb7kwhi

Low power RF IC design for wireless communication

Domine M.W. Leenaerts
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
Frequency Dividers Because the first stage of any frequency divider runs at the same frequency as the VCO and handles large signals, the design of this circuit is difficult and often consumes serious amounts  ...  The VCO of section 3.1 will be used, together with optimised frequency dividers. Figure 14 shows the die, occupying 1 mm 2 area in a 0.18 µm CMOS technology.  ... 
doi:10.1145/871506.871612 dblp:conf/islped/Leenaerts03 fatcat:qjjfjf6r6rhxpe4eqhmryvtu44

Low power RF IC design for wireless communication

Domine M.W. Leenaerts
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
Frequency Dividers Because the first stage of any frequency divider runs at the same frequency as the VCO and handles large signals, the design of this circuit is difficult and often consumes serious amounts  ...  The VCO of section 3.1 will be used, together with optimised frequency dividers. Figure 14 shows the die, occupying 1 mm 2 area in a 0.18 µm CMOS technology.  ... 
doi:10.1145/871611.871612 fatcat:njcceqqmpzawniz6nw36t4xmbe

Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer

Dawei Mai, Yann Donnelly, Michael Peter Kennedy, Stefano Tulisi, James Breslin, Patrick Griffin, Michael Connor, Stephen Brookes, Brian Shelly, Mike Keaveney
2022 IEEE Journal of Solid-State Circuits  
It describes a 4.9-GHz 180-nm SiGe BiCMOS charge-pump phase-locked loop (CP-PLL) fractional-N frequency synthesizer platform with a divider controller that can function as: 1) a standard MASH 1-1-1; 2)  ...  Fractional-N frequency synthesizers that use a digital -modulator (DDSM) to control the feedback divider can exhibit spurious tones that move about in the frequency domain; these are known colloquially  ...  When the modified MASH wandering spur solution with DT(z) = 2(1 − z −1 )z −2 is enabled, the amplitude envelope of the output phase noise short-term spectrum is reduced by more than 20 dB with a jitter  ... 
doi:10.1109/jssc.2022.3163080 fatcat:2m5nzqteojgophakkbtulq67xi

Chirp Generators for Millimeter-Wave FMCW Radars [chapter]

Dmytro Cherniak, Salvatore Levantino
2019 SpringerBriefs in Applied Sciences and Technology  
less than 200 ns with no over or undershoot after an abrupt frequency step.  ...  to achieve at the same time low phase noise and fast linear chirps.  ...  This setup reducing the output frequency to around 5.8 GHz simplifies both phase-noise measurement, which does not require external mixers, and modulation-analysis measurement, as it scales down by four  ... 
doi:10.1007/978-3-030-32094-2_3 fatcat:qcljmftu7zcrtmevyqypm5w3ny

A Direct Digital Frequency Synthesizer With Fourth-Order Phase Domain$DeltaSigma$Noise Shaper and 12-bit Current-Steering DAC

F.F. Dai, W. Ni, S. Yin, R.C. Jaeger
2006 IEEE Journal of Solid-State Circuits  
This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage 16 interpolator, and a 300-MS/s 12-bit current-steering DAC based on  ...  The implemented fourth-order single-stage 16 noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times.  ...  It is of significant commercial value to achieve very low phase noise frequency synthesis through DDFS due to its low cost and capability with digital CMOS integrations. B.  ... 
doi:10.1109/jssc.2006.870749 fatcat:q73m5gxnvzbjrbt23p7e3q2feq

System-on-Package MHMIC Milimeter-Wave Frequency Synthesizer for 60 GHz WPANs

Boris Spokoinyi, Rony E. Amaya, Ibrahim Haroun, Jim Wight
2012 International Journal of Microwave Science and Technology  
We present a low-cost millimeter-wave frequency synthesizer with ultralow phase noise, implemented using system-on-package (SoP) techniques for high-data-rate wireless personal area network (WPAN) systems  ...  The synthesizer has measured phase noise of -111.5 dBc/Hz at 1 MHz offset and integrated phase noise of 2.8° (simulated: 2.5°) measured at 57.6 GHz with output power of +1 dBm.  ...  Special thanks to Adrian Momciu for the help with manufacturing and testing.  ... 
doi:10.1155/2012/906516 fatcat:hxqes2akqncurnklgyeva2qzi4

System simulations of a 1.5 V SiGe 81–86 GHz E-band transmitter

Tobias Tired, Per Sandrup, Anders Nejdel, Johan Wernehag, Henrik Sjöland
2016 Analog Integrated Circuits and Signal Processing  
The presented design is based on a 28 GHz QVCO, the lower frequency reducing the phase error due to mismatch in active and passive devices.  ...  The EVM dependency on QVCO phase noise, I/Q imbalance and PA compression has been analyzed.  ...  In case of a residual phase error, this can be minimized using the I/Q phase tuning of the QVCO in Fig. 2 (a) [7, 8] .  ... 
doi:10.1007/s10470-016-0902-2 fatcat:lxcwcbsvxrfwncsfdr3adew4la
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