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Efficient dynamic heap allocation of scratch-pad memory

Ross McIlroy, Peter Dickman, Joe Sventek
2008 Proceedings of the 7th international symposium on Memory management - ISMM '08  
Modern dynamic memory management techniques are too heavy-weight for scratch-pad management.  ...  While there has been promising work in compile time allocation of scratch-pad memory, there will always be applications which require run-time allocation.  ...  Both of these concurrent implementations manage the 16kB IXP scratch-pad memory shared across the micro-engine cores.  ... 
doi:10.1145/1375634.1375640 dblp:conf/iwmm/McIlroyDS08 fatcat:vn27q242kvbbzjkmyb2grcixga

A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore

Julien Hascoe, Benoet Dupont de Dinechin, Karol Desnos, Jean-Francois Nezan
2018 2018 IEEE High Performance extreme Computing Conference (HPEC)  
Indeed, such processors comprise multiple compute units or clusters, each fitted with an on-chip local memory shared by several cores.  ...  While highly efficient OpenVX implementations exist for shared memory multi-core processors, targeting OpenVX to clustered manycore processors appears challenging.  ...  Red arrows show global main memory spaced [5] transfers to the distributed array of scratch-pad memories.  ... 
doi:10.1109/hpec.2018.8547736 dblp:conf/hpec/HascoetDDN18 fatcat:ri7iejxc2ffmhk3sntlilwxniq

The Impact of Higher Communication Layers on NoC Supported MP-SoCs

T. Marescaux, E. Brockmeyer, H. Corporaal
2007 First International Symposium on Networks-on-Chip (NOCS'07)  
Based on a realistic case study, we present a contrastive comparison of cache-based versus scratch-pad managed interprocessor communication for (distributed shared-memory) multiprocessor systems-on-chip  ...  The first version of the platform uses caches to perform inter-processor communication whereas the second one uses a novel type of distributed DMA to help performing scratch-pad management.  ...  Baert to the application mapping.  ... 
doi:10.1109/nocs.2007.41 dblp:conf/nocs/MarescauxBC07 fatcat:ywttd7pwzbhlnmtx76bzzhmzoi

Dynamic allocation for scratch-pad memory using compile-time decisions

Sumesh Udayakumaran, Angel Dominguez, Rajeev Barua
2006 ACM Transactions on Embedded Computing Systems  
A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache.  ...  (i) To reason about the contents of scratch-pad across time, it helps to attach a concept of time to the above-defined program points.  ...  An alternative that is instead prevalent is to use compiler managed SRAM or scratch-pad.  ... 
doi:10.1145/1151074.1151085 fatcat:6wqwhzbgkfbjzljrgim7cpod4m

Unified on-chip memory allocation for SIMT architecture

Ari B. Hayes, Eddy Z. Zhang
2014 Proceedings of the 28th ACM international conference on Supercomputing - ICS '14  
We first propose an unified on-chip memory allocation framework that uses scratch-pad memory to help: (1) alleviate single-thread register pressure; (2) increase whole application throughput.  ...  They are prone to making optimization decisions that benefit single thread but degrade the whole application performance.  ...  Another important type of on-chip memory is scratch-pad memory. It is referred to as shared memory in CUDA. For the rest of the paper, we use shared memory to refer to GPU scratch-pad memory.  ... 
doi:10.1145/2597652.2597685 dblp:conf/ics/HayesZ14 fatcat:rwc7y2txlrdd3fnkbueiuel6ce

Exploiting task-level concurrency in a programmable network interface

Hyong-youb Kim, Vijay S. Pai, Scott Rixner
2003 SIGPLAN notices  
Programmable network interfaces provide the potential to extend the functionality of network services but lead to instruction processing overheads when compared to application-specific network interfaces  ...  By carefully partitioning the handler procedures that process various events related to the progress of a packet, the system can minimize sharing, achieve load balance, and efficiently utilize on-chip  ...  The scratch pads, external SRAM, and other hardware registers are all mapped onto different memory address regions and form the Tigon memory address space.  ... 
doi:10.1145/966049.781506 fatcat:azlixmmn7rfctcg7sif74lpqti

Exploiting task-level concurrency in a programmable network interface

Hyong-youb Kim, Vijay S. Pai, Scott Rixner
2003 Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '03  
Programmable network interfaces provide the potential to extend the functionality of network services but lead to instruction processing overheads when compared to application-specific network interfaces  ...  By carefully partitioning the handler procedures that process various events related to the progress of a packet, the system can minimize sharing, achieve load balance, and efficiently utilize on-chip  ...  The scratch pads, external SRAM, and other hardware registers are all mapped onto different memory address regions and form the Tigon memory address space.  ... 
doi:10.1145/781503.781506 fatcat:vtiht72jl5eadm3pcmmywggzae

Exploiting task-level concurrency in a programmable network interface

Hyong-youb Kim, Vijay S. Pai, Scott Rixner
2003 Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '03  
Programmable network interfaces provide the potential to extend the functionality of network services but lead to instruction processing overheads when compared to application-specific network interfaces  ...  By carefully partitioning the handler procedures that process various events related to the progress of a packet, the system can minimize sharing, achieve load balance, and efficiently utilize on-chip  ...  The scratch pads, external SRAM, and other hardware registers are all mapped onto different memory address regions and form the Tigon memory address space.  ... 
doi:10.1145/781498.781506 dblp:conf/ppopp/KimPR03 fatcat:4dbjrzp37nfvplx5fe4jmppmcy

Compiler-directed scratch pad memory optimization for embedded multiprocessors

M. Kandemir, I. Kadayif, A. Choudhary, J. Ramanujam, I. Kolcu
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-Embedded systems, loop-dominated applications, scratch-pad memories (SPM).  ...  This is achieved by increasing the application-wide reuse of data that resides in scratch-pad memories of processors.  ...  ARCHITECTURE AND EXECUTION MODEL A virtually shared scratch pad memory (VS-SPM), is a shared SRAM space made up by individual SPMs of multiple processors.  ... 
doi:10.1109/tvlsi.2004.824299 fatcat:s3xlgfbbzngx7ghfpeqzfomxru

Management of Scratchpad Memory Using Programming Techniques

Kavita Tabbassum, Shahnawaz Talpur, Sanam Narejo, Noor-u-Zaman Laghari
2019 Mehran University Research Journal of Engineering and Technology  
as well as their applicability to numerous schemes of memory management are also discussed in this paper.  ...  In contrast to conventional caches in embedded schemes because of their better energy and silicon range effectiveness SPM (Scratch-Pad Memories) are being progressively used.  ...  from resident scratch memory.  ... 
doaj:7d10ffccc79a4b9180238ad3716a39eb fatcat:lw3nw4ovjnfbph4pbl3bw3epoq

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications

Doosan Cho, S. Pasricha, I. Issenin, N.D. Dutt, Minwook Ahn, Yunheung Paek
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
of a runtime scratch pad memory manager incorporated in the OS.  ...  Index Terms-Compiler optimizations, dynamic memory access pattern, multiprocessor system on chip (MPSoC), scratch pad memory (SPM).  ...  of a runtime scratch pad memory manager incorporated in the OS.  ... 
doi:10.1109/tcad.2009.2014002 fatcat:dhlcctxwxjavdehpujptcgacdm

Recursive function data allocation to scratch-pad memory

Angel Dominguez, Nghi Nguyen, Rajeev K. Barua
2007 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07  
A scratch-pad is a fast directly addressed compiler-managed SRAM memory that replaces the hardware-managed cache.  ...  With our method, all code, global, stack and heap variables can share the same scratch-pad.  ...  With our method, all code, global, stack and heap variables can share the same scratch-pad dynamically at runtime.  ... 
doi:10.1145/1289881.1289897 dblp:conf/cases/DominguezNB07 fatcat:3u6msndskvgt5fbh3ti2lnag6u

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Sumesh Udayakumaran, Rajeev Barua
2003 Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03  
A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardwaremanaged cache.  ...  In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory.  ...  The ARM968E-S has a dual-banked scratch-pad to store data and a DMA controller to share access to the scratch-pad memory.  ... 
doi:10.1145/951746.951747 fatcat:e5ml6sw54nhcdc6pq6nnij5hqa

Exploiting shared scratch pad memory space in embedded multiprocessor systems

M. Kandemir, J. Ramanujam, A. Choudhary
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
This is achieved by increasing the application-wide reuse of data that resides in the scratch-pad memories of processors.  ...  Our experimental results obtained on four array-intensive image processing applications indicate that exploiting inter-processor data sharing can reduce the energy-delay product by as much as 33.8% (and  ...  A virtually shared scratch pad memory (VS-SPM), on the other hand, is a shared SRAM space made up by individual SPMs of multiple processors.  ... 
doi:10.1109/dac.2002.1012623 fatcat:mff2myoconev3gc2oitpd53hgm

Exploiting shared scratch pad memory space in embedded multiprocessor systems

Mahmut Kandemir, J. Ramanujam, A. Choudhary
2002 Proceedings - Design Automation Conference  
This is achieved by increasing the application-wide reuse of data that resides in the scratch-pad memories of processors.  ...  Our experimental results obtained on four array-intensive image processing applications indicate that exploiting inter-processor data sharing can reduce the energy-delay product by as much as 33.8% (and  ...  A virtually shared scratch pad memory (VS-SPM), on the other hand, is a shared SRAM space made up by individual SPMs of multiple processors.  ... 
doi:10.1145/513972.513974 fatcat:itv4tcctqrf4rcwxuhicjfxk2i
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