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Bitonic Sorting on Dynamically Reconfigurable Architectures

J. Angermeier, E. Sibirko, R. Wanka, J. Teich
2011 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum  
This drawback concerns ASIC and statically reconfigurable systems.  ...  There are parallel sorting algorithms (sorting circuits) which are highly suitable for VLSI hardware realization and which outperform sequential sorting methods applied on traditional software processors  ...  On the FPGA, the de-serialization and serialization of the input and output data is done, respectively.  ... 
doi:10.1109/ipdps.2011.164 dblp:conf/ipps/AngermeierSWT11 fatcat:wkusx2k5evfqdceioxsteozyfu

Enabling Dynamic Communication for Runtime Circuit Relocation

Adewale Adetomi, Godwin Enemali, Tughrul Arslan
2019 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The clock buffers in a typical FPGA use independent wires and thus, do not constitute static routing.  ...  Runtime circuit relocation has been proposed for mitigating the effect of permanent damages in reconfigurable hardware like FPGAs with potentials to improve reliability and reduce or eliminate system downtime  ...  For instance, in [8] , the authors demonstrate bit-serial NoC routers that are 2-3x faster than their equivalent bit-parallel routers even with some level of pipeline optimization in the parallel implementation  ... 
doi:10.1109/tvlsi.2019.2934927 fatcat:mnsddiqkbnh25oyrn2eeeycpoq

Fpga Implementations Of Sorters For Non-Linear Filters

Boaz Hirschl, Leonid Yaroslavsky
2004 Zenodo  
The parallel rank computer has a fixed latency of two clock cycles. N Power Analysis The power consumed by the FPGA is divided into static and dynamic power consumption.  ...  Static power consummation is caused by a current leakage on the devices and can be found in the data sheet for the VIRTEX family. Switching of transistors causes dynamic power consumption.  ... 
doi:10.5281/zenodo.38189 fatcat:cjh5mw7dovgl7dpzhigr5danoi

Dynamic Partial Reconfigurable FIR Filter Design [chapter]

Yeong-Jae Oh, Hanho Lee, Chong-Ho Lee
2006 Lecture Notes in Computer Science  
FPGAs.  ...  The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various  ...  And each filter module consists of n/2 reconfigurable multiply-accumulate (rMAC) unit, which includes the serial-to-parallel register to get coefficient inputs in serial.  ... 
doi:10.1007/11802839_5 fatcat:r4pkitnat5gvdircdteyufix7i

Implementation of a FIR Filter on a Partial Reconfigurable Platform [chapter]

Hanho Lee, Chang-Seok Choi
2006 Lecture Notes in Computer Science  
This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs.  ...  Virtex FPGAs.  ...  Compared to the general symmetric FIR filter (GF), the slice number in reconfigurable FIR filter using DPR method was increased about 54% because of adding bus macro, serial-to-parallel register and a  ... 
doi:10.1007/11893011_14 fatcat:qe4km4m6qnckpb5shz5mofzrvy

FPGA technology for multi-axis control systems

Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jiménez, Aitzol Zuloaga
2009 Mechatronics (Oxford)  
In those systems, the trajectory generation software may run in powerful microprocessors embedded in the FPGA.  ...  In this case, the control IP core can be replaced dynamically by another module with another with different features.  ...  Zhao parallel [11], Zhao serial [11], Chen [10], Samet serial [9], Samet parallel [9] and Samet mixed Table 1 1 FPGA PID controller implementations Resources Zhao parallel [11] Zhao serial [11] Chen  ... 
doi:10.1016/j.mechatronics.2008.09.001 fatcat:kqlksy7dz5eqhnbkejauathbny

Design and Implementation of Reconfigurable Neuro-Inspired Computing Model on a FPGA

Basutkar Umamaheshwar Venkata Prashanth, Mohammed Riyaz Ahmed
2020 Advances in Science, Technology and Engineering Systems  
The architecture for design at device level offers the best possible design tradeoff for specific processor architectures and development choices.  ...  The various Intellectual Property (IP) cores are developed for the modules such as Block RAM, Differential Clock, Floating Point, and First In First Out (FIFO) for the design of the neuron model in Xilinx  ...  Acknowledgment The Authors wish to thank School of ECE, REVA University, Bengaluru, India for providing necessary facilities in carrying out this research work.  ... 
doi:10.25046/aj050541 fatcat:3pfny2go7feu3foe5lvr6po6qi

A Dynamically Reconfigurable System for Closed-Loop Measurements of Network Traffic

Faisal Khan, Soheil Ghiasi, Chen-Nee Chuah
2014 IEEE transactions on computers  
Streaming network traffic measurement and analysis is critical for detecting and preventing any real-time anomalies in the network.  ...  Our innovative dynamically reconfigurable socket offers 3Â logic savings over conventional static solutions, while offering much reduced reconfiguration latencies over conventional PDR mechanisms.  ...  Area Results We first compare the area resources taken of the proposed Socket (also referred to here as dynamic) with an equivalent static solution mapped on the same FPGA.  ... 
doi:10.1109/tc.2012.228 fatcat:beq7uzckerbmfgierzoumefaxm

The role of dynamic reconfiguration for implementing artificial neural networks models in programmable hardware [chapter]

J. M. Moreno, J. Cabestany, E. Cantó, J. Faura, J. M. Insenser
1999 Lecture Notes in Computer Science  
a Chip) offer an efficient altemative (both in terms of area and speed) for implementing hardware accelerators.  ...  After presenting the data flow associated with a serial arithmetic unit, we shall show how its dynamic implementation in the FIPSOC device is able to outperform systems realised in conventional programmable  ...  Acknowledgements This work is being carried out under the ESPRIT project 21625 and spanish CICYT project TIC-96-2015-CE.  ... 
doi:10.1007/bfb0100475 fatcat:vugg6aypxnepfacxbpdc25euby

A Novel Fingerprint SoC with Bit Serial FPGA Engine

Yiwen Wang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda
2005 IPSJ Digital Courier  
The paper presents firstly a novel system-on-chip (SoC) architecure consisting of a 32-bit RISC processor, on-chip memory, state-of-the art IPs and embedded full-custom bit serial FPGA (BSFPGA) I/O interface  ...  With RTL model for BSFPGA, it enables a timing simulation of the total system in RTL level and a timing verification in transistor level.  ...  Instead of designing special data converting circuit outside BSFPGA, parallel serial converter and serial parallel converter are inserted dynamically into application design.  ... 
doi:10.2197/ipsjdc.1.226 fatcat:orfssl3bevapzjcilrzv7fndvm

Parallelizing sparse Matrix Solve for SPICE circuit simulation using FPGAs

Nachiket Kapre, Andre DeHon
2009 2009 International Conference on Field-Programmable Technology  
-5 FPGA (65nm) and an Intel Core i7 965 processor (45nm).  ...  Matrix Solve is the dominant component of the simulator especially for large circuits and is invoked repeatedly during the simulation, once for every iteration.  ...  the performance of the FPGA solver with an equivalent parallel solver running on multicore processors and GPUs.  ... 
doi:10.1109/fpt.2009.5377665 fatcat:22q5j5nmajdvphn7kpeo6gtsem

Fpga Based Optimal Charging In a Solar Powered Robot

M. Ragulkumar, P. Manikandan, Dr G. K. D Prasanna Venkatesan
2014 IOSR Journal of VLSI and Signal processing  
FPGA Robotics is commonly used in a VANTER Robotics and space. An efficient solar power FPGA Robotic designs contains low power consumption and improved batteries life.  ...  However the solar panel powered rover introduces the concept of using FPGA for intelligent power management system.  ...  Current approaches to FPGA design do not allowed for easy reduction of dynamic or static power, although it possible to theoretically.  ... 
doi:10.9790/4200-04322933 fatcat:7icfij2u35gptkhr3rwrmoytxe

PID Controller Using FPGA Technology [chapter]

Abdesselem Trimeche, Anis Sakly, Abdelatif Mtibaa, Mohamed Benrejeb
2011 Advances in PID Control  
FPGAs [4] .  ...  of transistors for the most recent generations.  ...  The circuits for the PID controllers have been obtained by logic synthesis and place and route using Xilinx ISE 7.1i, from the VHDL representation generated by the static analyzer.  ... 
doi:10.5772/18295 fatcat:igs7yefb7vd2hesobhhmih7vh4

Artificial neural network implementation on a fine-grained FPGA [chapter]

P. Lysaght, J. Stockwood, J. Law, D. Girma
1994 Lecture Notes in Computer Science  
This allows a larger ANN to be implemented on a single FPGA at the expense of slower overall system operation.  ...  This paper reports on the implementation of an Artificial Neural Network (ANN) on an Atmel AT6005 Field Programmable Gate Array (FPGA).  ...  Acknowledgements The authors would like to thank the Nuffield Foundation, SERC and the Defence Research Agency for their support.  ... 
doi:10.1007/3-540-58419-6_126 fatcat:mkz3gavh3jdxpgqcaeq6bkwosq

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs

Paul Teehan, Guy G.F. Lemieux, Mark R. Greenstreet
2009 Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '09  
There may be an opportunity to use throughput-oriented interconnect to decrease routing congestion and wire area using on-chip serial signaling, especially for datapath designs which operate on words instead  ...  In particular, supply noise is a critical modeling challenge; better models are needed for FPGA power grids.  ...  for valuable feedback.  ... 
doi:10.1145/1508128.1508136 dblp:conf/fpga/TeehanLG09 fatcat:rof64hqeljagxhm7idt3xgkg4q
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