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Synthesis Optimization for Finite State Machine Design in FPGAs

Uma R
2012 International Journal of VLSI Design & Communication Systems  
The synthesis tool provides the selection of different constraint to optimize the circuit. This paper presents the design and synthesis optimization constraints in FPGA for Finite state machine.  ...  The primary goal of this sequential logic design is to optimize the speed and area by choosing the proper options available in the synthesis tool.  ...  To optimize the circuit at sequential level, state minimization and state assignment procedure are executed.  ... 
doi:10.5121/vlsic.2012.3607 fatcat:7hqgxurbkvbrvoduf6n5p5yv4i

New designs of reversible sequential devices [article]

Anindita Banerjee, Anirban Pathak
2009 arXiv   pre-print
Using that protocol, reversible circuits for SR latch, D latch, JK latch and T latch are designed from NCT gate library.  ...  In this context, some important conceptual issues related to the designing and optimization of sequential reversible circuits have been addressed.  ...  In section 5, we have provided a protocol for synthesis of reversible circuits we have also used it to design reversible sequential elements.  ... 
arXiv:0908.1620v1 fatcat:f6zxla7bnzbrnmx6jblxe5w6zy

Merging nodes under sequential observability

Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
By considering both the sequential nature of the design and observability simultaneously, better results can be obtained than with either algorithm alone.  ...  This paper presents a new type of sequential technology independent synthesis.  ...  In synthesis, technology independent optimizations are used before technology mapping, and there is a strong correlation between circuit sizes before and after mapping [2] .  ... 
doi:10.1145/1391469.1391605 dblp:conf/dac/CaseKMB08 fatcat:w5stse4uivgibegup3pzab3fka

Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs [chapter]

Laurent Arditi, Gerard Berry, Michael Kishinevsky
2004 Lecture Notes in Computer Science  
Esterel compilation deploys sequential optimization to improve delay and area of the netlist.  ...  We show that all sequential optimizations used in Esterel compilation can be made reversible and demonstrate that an ECO problem can be reduced to a commonly solved combinational ECO problem.  ...  We thank Chunduri Rama Mohan from Intel for posing the problem and Xavier Fornari and Marc Perreaut from Esterel Technologies for their help during this work.  ... 
doi:10.1007/978-3-540-30494-4_10 fatcat:avl6uafanbd55bc2fosmmvvtxm

An optimal algorithm for sizing sequential circuits for industrial library based designs

Roy Sanghamitra, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng
2008 2008 Asia and South Pacific Design Automation Conference  
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits.  ...  designs.  ...  INTRODUCTION Synchronous sequential circuits form the core of modern IC designs.  ... 
doi:10.1109/aspdac.2008.4483929 dblp:conf/aspdac/RoyHCHCT08 fatcat:s35yozcohbayfnabhcs2p5lhsy

EPR — a Synthesis Tool for Speed Optimization [chapter]

E. Fehlauer, St Rülke, G. Franke
1995 IFIP Advances in Information and Communication Technology  
Different sequential and combinational optimization techniques are combined together. Using EPR, complexity of the optimization task is broken down and bottlenecks of other approaches are removed.  ...  Key to EPR is the idea to compute optimal register positions in an iterative manner and only for selected circuit partitions at a time.  ...  The synthesis tools provide us not only with required algorithms for timing and area optimizations but also with facilities to obtain design analysis.  ... 
doi:10.1007/978-0-387-34920-6_15 fatcat:essueg2kgvcizpmeycq34i2c3m

Synthesis of Sequential Reversible Circuits through Finite State Machine [article]

Shubham Gupta
2015 arXiv   pre-print
Our propose designs of reversible counters are significantly better in optimization parameters such as gate counts, garbage outputs and constant inputs available in literature.  ...  One side is to propose a low cost reversible gate suitable for sequential building block i.e. T flip-flop and hence designing low cost synchronous and asynchronous counters.  ...  The synthesis and optimization technique of sequential reversible circuits is also proposed.  ... 
arXiv:1410.2370v3 fatcat:cnxml765tjhahoaesdtphrgrcq

TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits

Ebrahim M. Songhori, Siam U. Hussain, Ahmad-Reza Sadeghi, Thomas Schneider, Farinaz Koushanfar
2015 2015 IEEE Symposium on Security and Privacy  
We introduce TinyGarble, a novel automated methodology based on powerful logic synthesis techniques for generating and optimizing compressed Boolean circuits used in secure computation, such as Yao's Garbled  ...  Finally, our sequential description enables us to design and realize a garbled processor, using the MIPS I instruction set, for private function evaluation.  ...  David Evans for his very insightful comments, and anonymous reviewers for their helpful comments and suggestions to improve  ... 
doi:10.1109/sp.2015.32 dblp:conf/sp/SonghoriHS0K15 fatcat:qejhlavt2vgrncaufs352idf5i


Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert Brayton
2009 Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '09  
Meanwhile, academic research in logic synthesis has been fruitful, but these advances have been demonstrated on academic architectures and benchmark designs which are not representative of modern industrial  ...  This work is integrated into the Xilinx ISE 11.1 software flow for FPGAs and shows significant improvements in both the LUT count and performance of large industrial circuits described in HDL.  ...  ACKNOWLEDGEMENTS The authors wish to thank David Nguyen Van Mau, and Yassine Rjimati of Tiempo for their feedback and suggestions in conceiving and implementing this work.  ... 
doi:10.1145/1508128.1508165 dblp:conf/fpga/JangWJCCMB09 fatcat:hkcg4idnf5br5kbgg2upqla3mu

Optimizing equivalence checking for behavioral synthesis

Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation.  ...  We present a suite of optimizations for equivalence checking of RTL generated through behavioral synthesis.  ...  ACKNOWLEDGMENT This research was partially supported by National Science Foundation Grants #CCF-0916772 and #CCF-0917188 and by a research grant from Intel Corporation.  ... 
doi:10.1109/date.2010.5457049 dblp:conf/date/HaoXRY10 fatcat:jpkqm3ucvfbfbeguuc4jvxyzuy

Design of a logic synthesis system (tutorial)

Richard Rudell
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
Logic synthesis systems are c omplex systems and algorithmic research in synthesis has become highly specialized.  ...  This tutorial starts by describing a set of constraints which synthesis algorithms must satisfy to be useful.  ...  Behavioral synthesis, retiming, and other useful sequential optimizations cannot be veried using the formal verication techniques available today.  ... 
doi:10.1145/240518.240554 dblp:conf/dac/Rudell96 fatcat:nxhyi3cylrgnzdm7d27kvbhpwe

Automatic addition of reset in asynchronous sequential control circuits

Vikas S. Vij, Kenneth S. Stevens
2013 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)  
This approach is independent of design methodology since it is applied to a gate netlist. The algorithm ensures all combinational cycles and primary outputs in the circuit are initialized.  ...  Results are reported for applying this algorithm to designs of varying size and complexity.  ...  BACKGROUND Two significant holes currently exist in the CAD tools used for synthesis of sequential asynchronous circuit designs: technology mapping and reset generation.  ... 
doi:10.1109/vlsi-soc.2013.6673312 dblp:conf/vlsi/VijS13 fatcat:3knqjv5zlreenfxgmwsdfyimdi

Computer-aided design and optimization of control units for VLSI processors

Giovanni de Micheli
1988 International journal of circuit theory and applications  
This review presents the models. methods and algorithms for synthesis and optimization of control units for VLSI processors.  ...  First. circuit structures used for control in the state,.of-the-art processors are described.  ...  MIP-8710748 and by a seed grant of the Center for Integrated Systems at Stanford.  ... 
doi:10.1002/cta.4490160403 fatcat:dayg4no2dzgaffzuejfusvfvle

Optimal State Assignment for Finite State Machines

G. De Micheli, R.K. Brayton, A. Sangiovanni-Vincentelli
1985 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This allows the automation of FSM-based sequential-circuit design.  ...  Sequential circuits play a major role in the control part of digital systems. Digital computers are very complex examples of sequential systems and involve a combination of sequential functions.  ... 
doi:10.1109/tcad.1985.1270123 fatcat:wzmgse726bdmdkvu3vvzzvcepa

Using combinational verification for sequential circuits

Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
Retiming combined with combinational optimization is a powerful sequential synthesis method.  ...  We also demonstrate that our methodology covers a large class of circuits by applying it to a set of benchmarks and industrial designs.  ...  Perform synthesis for delay optimization and min-period retiming on the modified circuit (B) to obtain a new circuit (C). 3.  ... 
doi:10.1145/307418.307476 fatcat:sa2ih22kdretvgszwadwxualba
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