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JaVerT: JavaScript verification toolchain
2017
Proceedings of the ACM on Programming Languages
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dynamic features of JavaScript; JSIL Verify, a semi-automatic verification tool based on a sound JSIL separation logic; and verified axiomatic specifications of the JavaScript internal functions. ...
The dynamic nature of JavaScript and its complex semantics make it a difficult target for logic-based verification. ...
We reason efficiently about the fundamental dynamic features of JavaScript using JSIL Verify (V2), the first verification tool based on separation logic to natively support such features. ...
doi:10.1145/3158138
dblp:journals/pacmpl/SantosMNWG18
fatcat:t6uxa2t2pjesjmdl7hwinrj74q
A Machine Checked Soundness Proof for an Intermediate Verification Language
[chapter]
2009
Lecture Notes in Computer Science
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In our approach, we define a formal operational semantics of the intermediate verification language, and we prove the soundness of two translations separately: (1) the translation of the intermediate verification ...
Such verifiers split the generation of VCs in two (or even more) phases, using an intermediate verification language as the bridge between the programming language and logic. ...
This paper focuses on the first step, and gives a small example of the second step. In Section 2, we give a short introduction to the BoogiePL intermediate verification language [4] . ...
doi:10.1007/978-3-540-95891-8_51
fatcat:h66mobvpxrh4pedsexmzfmtwle
Why Just Boogie? Translating Between Intermediate Verification Languages
[article]
2016
arXiv
pre-print
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The verification systems Boogie and Why3 use their respective intermediate languages to generate verification conditions from high-level programs. ...
This paper describes a translation of Boogie into WhyML (Why3's intermediate language) that preserves semantics, verifiability, and program structure to a large degree. ...
Other intermediate languages for verification are Pilar [23] , used in the Sireum framework for SPARK; Silver [12] , an intermediate language with native support for permissions in the style of separation ...
arXiv:1601.00516v2
fatcat:ep5h32oa55bqvik4wdbufhnxui
A general formal memory framework in Coq for verifying the properties of programs based on higher-order logic theorem proving with increased automation, consistency, and reusability
[article]
2018
arXiv
pre-print
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We also implement a toy functional programming language in a generalized algebraic datatypes style and a formal interpreter in Coq based on the GERM framework. ...
In recent years, a number of lightweight programs have been deployed in critical domains, such as in smart contracts based on blockchain technology. ...
Appel and Blazy [32] later developed a mechanized separation logic for a C-based intermediate language in Coq. Manson et al. [29] developed a Java memory model. ...
arXiv:1803.00403v3
fatcat:jpgpzx5zxnbpbpzfdj7kowgee4
A Polymorphic Intermediate Verification Language: Design and Logical Encoding
[chapter]
2010
Lecture Notes in Computer Science
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Intermediate languages are a paradigm to separate concerns in software verification systems when bridging the gap between programming languages and the logics understood by theorem provers. ...
As a concrete solution, the paper presents the type system of Boogie 2, an intermediate verification language that is used in several program verifiers. ...
The intermediate verification language serves as a thinking tool in the design of the verifier front end for each particular source language. ...
doi:10.1007/978-3-642-12002-2_26
fatcat:5ghnjvv3vze3lmiebfa5pwl4ye
A Certifying Code Generation Phase
2007
Electronical Notes in Theoretical Computer Science
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A certifying compiler generates for each run a proof that it has performed the compilation run correctly. The proof is checked in a separate theorem prover. ...
Guaranteeing correctness of compilation is a vital precondition for correct software. Code generation can be one of the most error-prone tasks in a compiler. ...
One result of these steps is a mapping from intermediate language variables to registers and memory addresses (variable mapping). ...
doi:10.1016/j.entcs.2007.09.008
fatcat:nlupz6t4zvdqtouwp23l2m72wq
A General Formal Memory Framework for Smart Contracts Verification based on Higher-Order Logic Theorem Proving
2019
International Journal of Performability Engineering
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One of the most reliable methods for s the security and reliability of smart contracts is a formal symbolic virtual machine based on higher-order logic proof system. ...
It formalizes logic addresses, nonintrusive application programming interfaces, physical memory structures, and auxiliary tools in Coq. ...
Appel and Blazy presented mechanized separation logic for a C-based intermediate language using Coq [7] . Manson et al. developed a Java memory model [8] . ...
doi:10.23940/ijpe.19.11.p19.29983007
fatcat:obcrrcxhvfcb3cbx32xokv4nfq
RTL c-based methodology for designing and verifying a multi-threaded processor
2002
Proceedings - Design Automation Conference
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A RTL C-based design and verification methodology is presented which enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. ...
The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. ...
The definition of this design methodology involved the work of several members of the design and verification teams. ...
doi:10.1145/513918.513951
dblp:conf/dac/SemeriaMPESN02
fatcat:3w7rm3b2yrg7ljvc2uc5rkyeha
RTL c-based methodology for designing and verifying a multi-threaded processor
2002
Proceedings - Design Automation Conference
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A RTL C-based design and verification methodology is presented which enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. ...
The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. ...
The definition of this design methodology involved the work of several members of the design and verification teams. ...
doi:10.1145/513950.513951
fatcat:s3h3m2nudjfitphlzfkubh4mvq
RTL C-based methodology for designing and verifying a multi-threaded processor
2002
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
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A RTL C-based design and verification methodology is presented which enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. ...
The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. ...
The definition of this design methodology involved the work of several members of the design and verification teams. ...
doi:10.1109/dac.2002.1012606
fatcat:2otw277idfbg7lcekm6vlecmhm
Model Checking Object-Z Specification Using SPIN
2013
Sensors & Transducers
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Subsequently, the history invariant in Object-Z is described by Linear Temporal Logic (LTL). So the correctness of Object-Z specification can be verified. ...
However, it is difficult to establish a tool to directly verify Object-Z, because of its high-level abstraction. ...
State schema: Local variables and state variables are defined in a state schema, and the values of them at some time can be mapped to a state in LTS. ...
doaj:16ac689994a64f6f810c91cde1cc58b9
fatcat:xtwruo2c3ngtzm2dr4dqvcae7i
Participatory Verification of Railway Infrastructure by Representing Regulations in RailCNL
[chapter]
2017
Lecture Notes in Computer Science
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In order to allow railway engineers with limited logic programming experience to participate in the verification process, in this work we introduce a controlled natural language, RailCNL, which is designed ...
We also describe our design methodology, based on CNL best practices and previous experience with creating verification front-end languages. ...
We expand on these best practices in the context of creating intermediate languages for writing diverse natural text in a form which is translatable into formal verification properties. ...
doi:10.1007/978-3-319-66197-1_6
fatcat:uuofrmlf4neavhwmieddb7km24
Different Maps for Different Uses. A Program Transformation for Intermediate Verification Languages
[article]
2019
arXiv
pre-print
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In theorem prover or SMT solver based verification, the program to be verified is often given in an intermediate verification language such as Boogie, Why, or CHC. This setting raises new challenges. ...
We investigate a preprocessing step which takes the similar role that alias analysis plays in verification, except that now, a (mathematical) map is used to model the memory or a data object of type array ...
The analogue to pointers in an intermediate verification language are map indices, i.e., values that are used to read values from a map variable. ...
arXiv:1901.01915v1
fatcat:l2myi7d4mzeyrgbdl6h5q2item
The bedrock structured programming system
2013
Proceedings of the 18th ACM SIGPLAN international conference on Functional programming - ICFP '13
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It is based on a cross-platform core combining characteristics of assembly languages and compiler intermediate languages. ...
The abstraction level of these macros only imposes a compile-time cost, via the execution of functional Coq programs that compute programs in our intermediate language; but the run-time cost is not substantially ...
This material is based on research sponsored by DARPA under agreement number FA8750-12-2-0293. The U.S. ...
doi:10.1145/2500365.2500592
dblp:conf/icfp/Chlipala13
fatcat:y674nwei2vbr5as4aebk2mkgpa
Formal verification of ASM designs using the MDG tool
2003
First International Conference onSoftware Engineering and Formal Methods, 2003.Proceedings.
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Both ASM and MDG are based on a subset of many-sorted first order logic, making it appealing to link these two concepts. ...
If a variable is Boolean, the term is also Boolean. ¦ If f is an r § © function name in a given vocabulary and t ¢ t are terms, then f t ¢ t ! is a term. ...
We create these tables by mapping ASM models through the intermediate language into MDG-HDL tables along with variable order and algebraic specifications as shown in Figure 10 . ...
doi:10.1109/sefm.2003.1236223
dblp:conf/sefm/GawanmehTW03
fatcat:b6o4yyllxjfo5pwdjsboww2s6q
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