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Testing the 500-MHz IBM S/390 microprocessor

T.G. Foote, D.E. Hoffman, W.V. Huott, T.J. Koprowski, M.P. Kusko, B.J. Robbins
1998 IEEE Design & Test of Computers  
, cryptography, and connections for the level-three memory and S/390 I/O subsystem.  ...  I/O tests. We tested CMOS S/390 chips on reduced pin count testers both at the wafer and single-chip module level.  ...  He is currently responsible for definition and implementation of test strategy for the IBM S/390's storage control chips.  ... 
doi:10.1109/54.706038 fatcat:w3nfhg7wynbbjfgktjiw3gy3iu

The Integrated Cluster Bus for the IBM S/390 Parallel Sysplex

T. A. Gregg, K. M. Pandey, R. K. Errickson
1999 IBM Journal of Research and Development  
IBM has developed a new S/390 ® Parallel Sysplex ® coupling interface for the G5 server called the Integrated Cluster Bus (ICB).  ...  Using the transport layer of the S/390 selftimed interface (STI) introduced in the G3 server, ICB adds channel function to the hub chip to allow a more direct interconnection between S/390 servers.  ...  Special acknowledgment goes to Lothar Klein and Elke Nass for their microcode skills, and to Norbert Schumacher for his hub chip design and  ... 
doi:10.1147/rd.435.0795 fatcat:royjkwsd6vh5nb2ehpcpahirxi

The role of two-cycle simulation in the S/390 verification process

Gary A. Van Huben
1997 IBM Journal of Research and Development  
Microprocessor design techniques have evolved to a point where large systems, such as S/390@ servers, can be constructed using relatively few, but very complex, applicationspecific integrated circuits  ...  The aggressive design schedule undertaken on the S/390 Parallel Enterprise Server G4 program required additional advances in simulation beyond those employed in the development of the IBM Enterprise System  ...  The following people also deserve mention for their outstanding contributions in the areas of two-cycle verification as well as for providing valuable information for this paper:  ... 
doi:10.1147/rd.414.0593 fatcat:ub56vtqinzaq5ovhypw3b6cdla

Multiple-logical-channel subsystems: Increasing zSeries I/O scalability and connectivity

L. W. Wyman, H. M. Yudenfriend, J. S. Trotter, K. J. Oakes
2004 IBM Journal of Research and Development  
Essential to an increased processing capacity is the corresponding need for significant increases in total I/O scalability and connectivity.  ...  With the z990, increased I/O capacity is provided by increasing the number of physical I/O channels that can be configured to the system and by restructuring the physical channel subsystem (CSS) into logically  ...  The multipleimage facility (previously supported by some S/390 and all previous z/Architecture models) that is associated with each channel-subsystem image provides for the replication of both channel-path  ... 
doi:10.1147/rd.483.0489 fatcat:o6zyvrm7ozbcdomt4rmhuyrkue

First- and second-level packaging for the IBM eServer z900

H. Harrer, H. Pross, T.-M. Winkel, W. D. Becker, H. I. Stoller, M. Yamamoto, S. Abe, B. J. Chamberlin, G. A. Katopis
2002 IBM Journal of Research and Development  
The high-frequency requirements of this design due to operating frequencies of 918 MHz for on-chip and 459 MHz for off-chip interconnects make a comprehensive design methodology and post-routing electrical  ...  This paper describes the system packaging of the processor cage for the IBM eServer z900.  ...  to the I/O subsystem.  ... 
doi:10.1147/rd.464.0397 fatcat:6skl6bea2bhc3pzhub2pmzsvmu

Reliability, availability, and serviceability (RAS) of the IBM eServer z990

M. L. Fair, C. R. Conklin, S. B. Swaney, P. J. Meaney, W. J. Clarke, L. C. Alves, I. N. Modi, F. Freier, W. Fischer, N. E. Weber
2004 IBM Journal of Research and Development  
In order to continue to support the zSeries legacy for high availability and continuous reliable operation, the z990 delivers significant new features for reliability, availability, and serviceability  ...  This paper describes these new capabilities, in each case presenting the value of the feature, both in terms of enhancing the self-management capability of the server and its availability.  ...  Hardware view The channel subsystem structure comprises CPs, SAPs, MBAs, enhanced self-timed interface (eSTI) ports, and the high-density I/O cage.  ... 
doi:10.1147/rd.483.0519 fatcat:lcubvnb5zzd6nlxpjdfgklrrbq

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems

J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B.-L. Chu, M. L. Behm, J. R. Baumgartner, R. D. Peterson, J. Abdulhafiz, W. E. Bucy, J. H. Klaus (+13 others)
2002 IBM Journal of Research and Development  
Multi-unitlevel verification, performed on storage and I/O components as well as on the processor, confirmed architectural compliance for each of the chips and subsystems.  ...  The approach was hierarchical, based on but considerably expanding the practice used for verification of the CMOS-based IBM S/390 Parallel Enterprise Server TM G4.  ...  Ludden initially was involved in the verification of I/O and storage control subsystems for IBM S/390 mainframes.  ... 
doi:10.1147/rd.461.0053 fatcat:474llttpkvghngwg4q6veuhvqq

First- and second-level packaging of the z990 processor cage

T.-M. Winkel, W. D. Becker, H. Harrer, H. Pross, D. Kaller, B. Garben, B. J. Chamberlin, S. A. Kuppinger
2004 IBM Journal of Research and Development  
blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed  ...  interface (STI) cables plugged into the front of the node.  ...  Acknowledgment The authors would like to thank Roland Frech for performing the VHDM connector measurements and for providing the coupling data in Table 4 .  ... 
doi:10.1147/rd.483.0379 fatcat:hr27o73sjjas7ii7km6q3suk7m

IBM POWER7 multicore server processor

B. Sinharoy, R. Kalla, W. J. Starke, H. Q. Le, R. Cargnoni, J. A. Van Norstrand, B. J. Ronchetti, J. Stuecheli, J. Leenstra, G. L. Guthrie, D. Q. Nguyen, B. Blaner (+3 others)
2011 IBM Journal of Research and Development  
A new memory interface using buffered double-data-rate-three DRAM and improvements in reliability, availability, and serviceability are discussed.  ...  The memory subsystem contains three levels of on-chip cache, with SOI embedded dynamic random access memory (DRAM) devices used as the last level of cache.  ...  memory and I/O subsystems.  ... 
doi:10.1147/jrd.2011.2127330 fatcat:kztcasllyvgs5cuvzyf54myeyy

BladeCenter chassis management

T. Brey, B. E. Bigelow, J. E. Bolan, H. Cheselka, Z. Dayar, J. M. Franke, D. E. Johnson, R. N. Kantesaria, E. J. Klodnicki, S. Kochar, S. M. Lardinois, C. A. Morrell (+3 others)
2005 IBM Journal of Research and Development  
At the heart of the system is the management module hardware and firmware that provides chassis management for all components, thereby removing the cost and complexity of having to manage each component  ...  During his career at IBM he has worked on several different products, including S/390 I/O subsystems, AS/400* I/O processor development, and xSeries systems management. Mr.  ...  I/O switch module management This section describes how the MM and the control point (CPU subsystem) in an I/O switch module work together to provide systems management in a BladeCenter chassis.  ... 
doi:10.1147/rd.496.0941 fatcat:fs4svus7rjdxrme7fj2s5rgrwq

Functional verification of the z990 superscalar, multibook microprocessor complex

D. G. Bair, S. M. German, W. D. Wollyung, E. J. Kaminski, J. Schafer, M. P. Mullen, W. J. Lewis, R. Wisniewski, J. Walter, S. Mittermaier, V. Vokhshoori, R. J. Adkins (+3 others)
2004 IBM Journal of Research and Development  
Since the methods used at system-level verification were much the same as the ones used on the CMOS-based IBM S/390 Parallel Enterprise Server G4, the focus of this paper is on the work done at the unit  ...  The ring-based, four-book storage subsystem links 64 superscalar microprocessors together in this system.  ...  Acknowledgments The authors acknowledge all z990 design team members and other individuals throughout IBM for their contributions to the verification effort.  ... 
doi:10.1147/rd.483.0347 fatcat:c7pqoghcxzawbpgskfqe3jvs4y

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

J. U. Knickerbocker, P. S. Andry, L. P. Buchwalter, A. Deutsch, R. R. Horton, K. A. Jenkins, Y. H. Kwark, G. McVicker, C. S. Patel, R. J. Polastre, C. D. Schuster, A. Sharma (+8 others)
2005 IBM Journal of Research and Development  
The bulk of her professional career has focused on adhesion and related fields as they pertain to microelectronics conductor/insulator interfaces, in particular the adhesion of polyimide to inorganic surfaces  ...  Tornello for their help in SOP process learning and modeling, and to the MRL teams for their support of hardware build processing during the SOP research and development stages of this paper.  ...  This advance using l-C4 interconnection represents a 16 times improvement in I/O area density over a standard flip-chip array with 200-lm pitch.  ... 
doi:10.1147/rd.494.0725 fatcat:ixjfub2aobftpgs6ol7vvx3q3u

The circuit and physical design of the POWER4 microprocessor

J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, C. J. Anderson
2002 IBM Journal of Research and Development  
It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem.  ...  The main deliveries from any block owner at this time are "contracts." Contracts are the early size and timing budgets IBM Abstract Netlists Spice Noise rule Layout Custom macros Reports  ...  A process of iteration is used to create the final allocations for the signal I/O wires, clock distribution, and power.  ... 
doi:10.1147/rd.461.0027 fatcat:wp4ojp7zyfam5nhtajbfdfh2uy

The IBM PCIXCC: A new cryptographic coprocessor for the IBM eServer

T. W. Arnold, L. P. Van Doorn
2004 IBM Journal of Research and Development  
For the first time, a single product satisfies all requirements across all IBM server platforms.  ...  These began as very simple devices, but over time the requirements have become increasingly complex, and there has been a never-ending demand for increased speed.  ...  This architecture allows the I/O (crypto and communication) to be overlapped by computations and provide a traditional blocking programming model.  ... 
doi:10.1147/rd.483.0475 fatcat:5j64tgvjrfekthkazks22fcxnu

Ambysemy and eurisemy as phenomena in term semantic structure (Based on English IT-terminology)
Проявление амбисемии и эврисемии в семантической структуре термина (на материале английской IT-терминологии)

Lyudmila S. Yefremova, Saratov State University
2021 Izvestiya of Saratov University New Series Series Philology Journalism  
A run-time environment is an execution environment. Rusty Bucket n. An IBM headquarters facility in Bethesda, Maryland; often shortened to "The Bucket." S S/390 n.  ...  Examples of enterprise servers include the IBM S/390 family of servers. Enterprise Systems Connection (ESCON) n.  ...  WinSock application programming interface (API) n. A socket-style transport interface developed for the Windows family of operating systems. wire fault n.  ... 
doi:10.18500/1817-7115-2021-21-2-155-160 fatcat:idlxm4kawbbvrdu6hj4mrggv3u
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