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Self-timed full adder designs based on hybrid input encoding
2009
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
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Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are described in this paper. ...
Comparisons have been carried out with respect to various self-timed full adder designs which employ only a single widely used delay-insensitive input encoding for both the inputs and outputs. ...
ADDER DESIGNS BASED ON HYBRID INPUT ENCODING The hybrid input encoding (HIE) approach comprises of two different encoding schemes, adopted for the adder inputs: 1-of-4 encoding scheme for the augend and ...
doi:10.1109/ddecs.2009.5012099
dblp:conf/ddecs/BalasubramanianEB09
fatcat:o7kl5q2oendf3gcsj5b45ixqyi
HYBRID-CMOS LOGIC STYLE DESIGN FOR FAST SELF-CHECKING ADDERS DATA PATHS
2013
INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY
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In this paper we present an efficient design for self-checking fast adders data paths. ...
To achieve a low overhead, low power design, we use hybrid-CMOS logic style and combine Conventional CMOS and CMOS Pass transistor Logic (CPL). The proposed schemes are Totally Self-Checking (TSC). ...
It presents a self checking fast adder based on the use of double-rail and parity encoding to achieve the totally self checking goal.
II. BACKGROUND
II.1. ...
doi:10.24297/ijct.v10i6.7025
fatcat:4hg53gkqxbejhfklop373yyfbu
Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder
[article]
2019
arXiv
pre-print
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Compared to existing asynchronous adders corresponding to various architectures such as ripple carry adder (RCA), conventional carry lookahead adder (CCLA), carry select adder (CSLA), BCLARC, and hybrid ...
(RTZ) and 4-phase return-to-one (RTO) handshaking. ...
Edwards, “A delay efficient robust self-timed full adder,”
Proceedings of IEEE 3rd International Design and Test Workshop, pp. 129-134,
December 2008.
40. P. ...
arXiv:1903.09433v1
fatcat:5vswc63rb5hzrmqlea23hxxubu
Low power self-timed carry lookahead adders
2013
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)
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of self-timed section-carry based carry lookahead (SCBCLA) adders. ...
Cell based self-timed synthesis of recursive carry lookahead adders (RCLA) utilizing generate, propagate and kill functions is described in this paper, and are compared with the recently proposed designs ...
based on a subset of inputs. ...
doi:10.1109/mwscas.2013.6674684
dblp:conf/mwscas/Balasubramanian13
fatcat:gjzxmssjavakbjz73hvsi4zc4i
Self-Repairing Hybrid Adder with Hot-Standby Topology using Fault-Localization
2020
IEEE Access
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In this paper, a self-checking and repairing hybrid adder (HA) design with reduced area and time overhead is proposed. ...
The relationship between input and output bits of full adder was utilized for self-checking. Consider a full adder with inputs A, B, C in , and the outputs Sum, C out , as shown in Fig. 1(c) . ...
He is also currently serving on the editorial board of IEEE Transactions on Biomedical Circuits and Systems and the IEEE Transactions on Electron Devices (TED). ...
doi:10.1109/access.2020.3016427
fatcat:ti6bhp2fkrblzcwyv2m6t2zmli
Designs protracted to combinational and sequential circuits by using hybrid MOS transistor with memristor
2021
International Journal of Advanced Technology and Engineering Exploration
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Finally, it is used in full adder design. The average power dissipation is reduced by 69.32%. ...
Thus, researchers worked on a combination of memristor and MOS transistor affords with reduced area exploitation, reduced power dissipation, reliability, and large density. ...
Thus, the proposed full adder is designed using hybrid CMOS with memristor circuits. ...
doi:10.19101/ijatee.2021.874470
fatcat:j7ax4okotzc63dujoy6ah5fxlu
Area Efficient Computing-in-Memory Architecture Using STT/SOT Hybrid Three Level Cell
2022
IEEE Open Journal of Nanotechnology
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Moreover, the performance of the STT/SOT-TLC-based MFA is compared with other full adder designs. ...
This paper focuses on using spin-transfer torque (STT)/spin-orbit torque (SOT) based hybrid three-level cell (TLC) in CiM application for implementing logic circuits such as AND, XOR, and magnetic full ...
Transient analysis of magnetic full adder for input combinations of (a) 010 (b) 111. .
FIGURE 9 .FIGURE 10 . 910 FIGURE 9. ...
doi:10.1109/ojnano.2022.3166959
fatcat:dcccn5vnyrfq5iciwb5jx4xkfi
Global versus Local Weak-Indication Self-Timed Function Blocks - A Comparative Analysis
[article]
2016
arXiv
pre-print
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that is characteristic of a weak-indication self-timed design. ...
A self-timed ripple carry adder is considered as an example function block for the analysis. ...
A similar inference is likely to be made when considering local and global weak-indication self-timed RCAs constructed using a cascade of hybrid input encoded full adders [36] or homogeneous or heterogeneously ...
arXiv:1603.07962v1
fatcat:dph6tnkv5ze3pdt6mtbggg4atm
0.5 V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology
1998
Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98
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50 nm T-Gate transistors, if a new adder with a differential Manchester chain including special accelerators and if the DIGILOG multiplier, a leading-one-first pseudo-log multiplier with complexity order ...
ABSTRACT High-performance CMOS logic at a very low voltage of 0.5 V can deliver 150 Million 8x8 multiplications/s at an energy level of only 30fJ, if 0.35 µm SOI technology is enhanced with self-aligned ...
When using 0.8 mm SOI hybrid T-Gate transistors in the 8-Bit adder, time and energy consumed for one addition are 7 ns and 80 fJ, respectively. ...
doi:10.1145/280756.280810
dblp:conf/islped/DudekGHS98
fatcat:wf75mxg7e5dktkkzzzntk52yv4
A novel approach to perform reversible addition/subtraction operations using deoxyribonucleic acid
2014
2014 IEEE International Symposium on Circuits and Systems (ISCAS)
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In this paper, we propose a new approach for designing DNA-based reversible adder/subtractor circuit; it's possible to perform addition and subtraction operations using single circuit representation. ...
Traditional silicon computers consume much more power compared to computing systems based on Deoxyribonucleic Acid (DNA). In addition, DNA-based logic gates are stable and reusable. ...
However, existing DNA-based design [17] shows cleaver approach to encode 0/1 logic using two types of single DNA strands, one for input bit and another for operand bit. ...
doi:10.1109/iscas.2014.6865513
dblp:conf/iscas/SarkerB014
fatcat:e7niatfc7vg47p7kvyl5bnlc6y
Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic
2017
arXiv
pre-print
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The adders were realized and the simulations were performed based on a 32/28nm CMOS process. ...
All the asynchronous CLAs are quasi-delay-insensitive designs which incorporate the delay-insensitive dual-rail data encoding and adhere to the 4-phase return-to-zero handshaking. ...
The SOL based on [24] or [25] is the same and occupies 34.56µm 2 of silicon. Group3 comprises a regular RCLA based on [22] and a RCLA-RCA hybrid based on [22] and [12] . ...
arXiv:1710.05470v1
fatcat:pgo2ld5bw5acpin2mdk7jhg22q
Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications
2015
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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A delay model based on signal propagation path is proposed for more precise estimation of critical path delay of MCM blocks than the conventional adder depth and the number of cascaded full adders. ...
A genetic algorithm (GA)-based technique is further proposed to search for optimum additional fundamentals. ...
For example, if it takes ns to compute , then the time needed to compute is , instead of . Here, could be the delay just one or a few full adders, which depends on the adder structure. ...
doi:10.1109/tcsi.2014.2377412
fatcat:pkteumcs2nfhjno33yq75yblae
Performance Analysis of Transient Fault-Injection and Fault-Tolerant System for Digital Circuits on FPGA
2020
International Journal of Advanced Computer Science and Applications
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The FIS includes Berlekamp Massey Algorithm (BMA) based LFSRs, with fault logic followed by one -hot-encoder register, which generates the faults. ...
The four different MVL approaches are designed in the TMR module for digital circuits. The FIS-FTS module is designed on Xilinx-ISE 14.7 environment and implemented on Artix-7 FPGA. ...
The TMR based modules can control the commonmode SETs failures. The dual modular redundancy acts as self-voter logic and has two inputs and one output. ...
doi:10.14569/ijacsa.2020.0110516
fatcat:tyjczfj6sjcztk2er3pjz2zhx4
DNA-based molecular architecture with spatially localized components
2013
Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13
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This paper proposes practical spatial isolation of components, leading to more easily designed DNA-based circuits. ...
We believe that it is time for the computer architecture community to take notice and contribute. ...
We next compare working circuits: a half-adder, a full adder, and an n-bit full adder. ...
doi:10.1145/2485922.2485938
dblp:conf/isca/MuscatSCS13
fatcat:kg3iqjd5znh43hb55geyj3dvhi
DNA-based molecular architecture with spatially localized components
2013
SIGARCH Computer Architecture News
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This paper proposes practical spatial isolation of components, leading to more easily designed DNA-based circuits. ...
We believe that it is time for the computer architecture community to take notice and contribute. ...
We next compare working circuits: a half-adder, a full adder, and an n-bit full adder. ...
doi:10.1145/2508148.2485938
fatcat:cxibidg7jfffzcqsrq4orrvv6e
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