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Self-aligned double patterning layout decomposition with complementary e-beam lithography

Jhih-Rong Gao, Bei Yu, David Z. Pan
2014 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)  
boundaries › Post Processing Based Layout Decomposition › Simultaneous SADP+EBL Optimization t Experimental Results t Conclusion 2 Self-Aligned Double Patterning (SADP) 3 Target layout  ...  Borodovsky, Maskless Lito and Multibeam Mask Workshop, 2010 ] 193nm immersion Complementary Lithography 1 base mask + 4 cut masks 1 base mask + E-beam 11nm node Complementary/Hybrid Lithography  ... 
doi:10.1109/aspdac.2014.6742880 dblp:conf/aspdac/GaoYP14 fatcat:dys4xcenozeuplo77cyvfrtjxi

Dealing with IC manufacturability in extreme scaling

Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-seok Yang, Kun Yuan, Minsik Cho, David Z. Pan
2012 Proceedings of the International Conference on Computer-Aided Design - ICCAD '12  
The nanopatterning through the 193nm lithography is being pushed to its limit, through double/triple or more general multiple patterning, while non-conventional lithography technologies such as extreme  ...  ultra-violet (EUV), e-beam direct-write (EBDW), and so on, still have grand challenges to be solved for their adoption into IC volume production.  ...  Recently, [19] [20] [21] [22] proposed several algorithms for the self-aligned double patterning (SADP) type DPL decomposition problem.  ... 
doi:10.1145/2429384.2429430 dblp:conf/iccad/YuGDBYYCP12 fatcat:txbiun44a5d4loroiimr4nllie

Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography

Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou
2015 The 20th Asia and South Pacific Design Automation Conference  
As the feature size keeps scaling down and the circuit complexity increases rapidly, a more advanced hybrid lithography, which combines multiple patterning and e-beam lithography (EBL), is promising to  ...  In this paper, we formulate the layout decomposition problem for this hybrid lithography as a minimum vertex deletion K-partition problem, where K is the number of masks in multiple patterning.  ...  Yifang Chen from State Key Lab. of ASIC and System in Fudan University for providing the EBL system data and calculating the e-beam exposure time. We would like to thank Prof.  ... 
doi:10.1109/aspdac.2015.7059082 dblp:conf/aspdac/YangLZYZZ15 fatcat:ib2xkhas45gqlb7mxfhulzkvzy

Critical Review of Current Trends in ASIC Writing and Layout Analysis

Abhishek Vikram, Vineeta Agarwal
2016 JSTS Journal of Semiconductor Technology and Science  
Electrical Designs for Application Specific Integrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography.  ...  The results have been discussed with few example design features from the 28nm design layout.  ...  Various approaches have broken down the processing challenges, popular among them beingdouble patterning without hard mask, double patterning with hard mask, and self aligned double patterning.  ... 
doi:10.5573/jsts.2016.16.2.236 fatcat:muifwi3hdfgklbydoncjos4pni

Germanium Quantum-Dot Array with Self-Aligned Electrodes for Quantum Electronic Devices

I-Hsiang Wang, Po-Yu Hong, Kang-Ping Peng, Horng-Chih Lin, Thomas George, Pei-Wen Li
2021 Nanomaterials  
Multiple Ge QDs with good tunability in QD sizes and self-aligned electrodes were controllably achieved.  ...  combination of lithographic patterning and self-assembled growth.  ...  Nomenclature Abbreviations Full Names BG barrier gate CMOS complementary metal-oxide-semiconductor CB coupling barrier DQDs double quantum dots EBL electron-beam lithography EELS electron  ... 
doi:10.3390/nano11102743 pmid:34685184 fatcat:as6cz7nuhrebbnqk3dn2oddqsq

Review of computational lithography modeling: focusing on extending optical lithography and design-technology co-optimization

Kafai Lai
2012 Advanced Optical Technologies  
Competitive scaling requires two types of complementary models: fast predictive empirical models that can be used for pattern correction and verification; rigorous physical models that can be used to identify  ...  Today, all computational lithography efforts such as the optical proximity correction (OPC) and the optical rules check (ORC) depend on the ability to predictively model the lithography and metrology processes  ...  Figure 16 (A) The simulation of self-aligned patterns from diblock polymer lines in a narrow prepatterned trench.  ... 
doi:10.1515/aot-2012-0037 fatcat:ntz6nskdwffjjisayo7wqfldsq

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Rani S. Ghaida, Puneet Gupta
2012 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Such a framework can be used to co-evaluate and co-optimize design rules, patterning technologies, layout methodologies, and library architectures.  ...  in terms of major layout characteristics of area, manufacturability, and variability.  ...  (DPT) including Pitch-Split Double-Patterning Technology (PS-DPT) and Self-Aligned Double Patterning (SADP), a.k.a.  ... 
doi:10.1109/tcad.2012.2192477 fatcat:3ladiics3jc5bilabix6a4cx2e

The Challenges of Advanced CMOS Process from 2D to 3D

Henry Radamson, Yanbo Zhang, Xiaobin He, Hushan Cui, Junjie Li, Jinjuan Xiang, Jinbiao Liu, Shihai Gu, Guilei Wang
2017 Applied Sciences  
The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future  ...  Nowadays, 193 nm ArF immersion with self-aligned double patterning and self-aligned quadruple patterning techniques are used for lithography of 22 nm node and beyond.  ...  Process Integration of New Transistor Architecture In process flow for FinFETs, dense fins are patterned by using self-aligned double patterning (SADP), followed by oxide filling, planarization, and recessing  ... 
doi:10.3390/app7101047 fatcat:btsrot53grcd7noefvqfpfsnwa

Dimensional metrology and positioning operations: basics for a spatial layout analysis of measurement systems [article]

A. Lestrade
2011 arXiv   pre-print
This lecture gives the basic tools to designers in the field of measure by analysing the spatial layout of measurement systems since it is central to dimensional metrology as well as positioning operations  ...  Differential measurements with magnification: a link with reversal layout Some layouts allow the measurement of the double of a physical quantity to be measured.  ...  Self-calibration methods of stages dedicated to lithography in the semiconductor industry are based on the use of a lattice of invariant points defined by its symmetries [8] .  ... 
arXiv:1104.0799v1 fatcat:53jj35tpyjc4dmtpexqsv3g5l4

Electric Double Layer Capacitor [chapter]

2016 Encyclopedia of Nanotechnology  
CAD layout is designed accordingly. Patterns are written by an e-beam lithography tool using low current (~1 nA).  ...  The figure on the bottom shows the summed contribution of the GHOST pattern and the line pattern [5] Electron Beam Lithography (EBL) 1047 E Electron Beam Lithography Systems Although they all are based  ...  The next step in the fabrication of the EUV masks is the mask patterning by electron beam writing and dry etching.  ... 
doi:10.1007/978-94-017-9780-1_100279 fatcat:bwewyikjfjckhfucz5ta2fhg7a

Electronic Properties [chapter]

2016 Encyclopedia of Nanotechnology  
CAD layout is designed accordingly. Patterns are written by an e-beam lithography tool using low current (~1 nA).  ...  The figure on the bottom shows the summed contribution of the GHOST pattern and the line pattern [5] Electron Beam Lithography (EBL) 1047 E Electron Beam Lithography Systems Although they all are based  ...  The next step in the fabrication of the EUV masks is the mask patterning by electron beam writing and dry etching.  ... 
doi:10.1007/978-94-017-9780-1_100299 fatcat:uafi4jywlrhfxdtcrlnvzgboti

MEMS Technologies for Energy Harvesting [chapter]

Manuel Domínguez-Pumar, Joan Pons-Nin, Juan A. Chávez-Domínguez
2016 Nonlinearity in Energy Harvesting Systems  
Mechanisms to produce bistable potential will be studied, such as by placing fixed magnets, buckling of beams, or by using slightly slanted clamped-clamped beams.  ...  The chapter begins with a general introduction to the most common MEMS fabrication processes.  ...  Fig. 13 13 Bistable mechanism of double curved beams, [23] , a) initial stable position, b) applied force deflects the double beams, c) more force generates more deflection, d) beams at the second stable  ... 
doi:10.1007/978-3-319-20355-3_2 fatcat:zy7ysgat2jeddauku6b66nsnrm

Comparative Analysis of CMOS OTA

Shireen T. Sheikh
2012 IOSR Journal of VLSI and Signal processing  
Looking at future technology nodes, lithography friendly routing needs to support double patterning lithography in 32-22nm nodes, where robust layout decomposition and overlay error are critical issues  ...  (OPC), immersion lithography, and probably double patterning.  ...  The sum of intensities of edges E( k ) included in the enhanced image is calculated by the following expression: E( K ) = ∑ x ∑ y √ ᵟh k (x ,y) 2 + ᵟv k (x ,y) 2 ᵟh k (x, y) = g k (x+1, y-1) + g k (x +  ... 
doi:10.9790/4200-0130105 fatcat:gntbzbq7snfrnkyblkgfx3gyja

Technical Design Report for the: PANDA Micro Vertex Detector [article]

PANDA Collaboration: W. Erni, B. Krusche, Q. Wang, F. Feldbauer , H. Koch, J. Pychy, T. Trifterer, S. Bianco, R. Jäkel, R. Schnell , Th. Würschig , M. Caprini, M. De Napoli, N. Idzik, E. Bialkowski (+167 others)
2012 arXiv   pre-print
This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment.  ...  The FE-I3 has been tested with the digital readout board A, the ToPix v2 with both the readout boards A and B.  ...  been partially supported by the European Community Research Infrastructure Integrating Activity: HadronPhysics2 (grant agreement n. 227431) under the Sixth and Seventh Framework Program, DIRAC secondary beams  ... 
arXiv:1207.6581v2 fatcat:qjbrupqhrna5phsezkqxyeuhhy

Progress and perspectives in dry processes for nanoscale feature fabrication: fine pattern transfer and high-aspect-ratio feature formation

Taku Iwase, Yoshito Kamaji, Song Yun Kang, Kazunori Koga, Nobuyuki Kuboi, Moritaka Nakamura, Nobuyuki Negishi, Tomohiro Nozaki, Shota Nunomura, Daisuke Ogawa, Mitsuhiro Omura, Tetsuji Shimizu (+8 others)
2019 Japanese Journal of Applied Physics  
Atomic scale precision below 10 nm is now possible with fine patterning technologies for high-volume manufacturing of semiconductor devices.  ...  Here we conduct a systematic review of the literature over the last 40 years to evaluate the history and progress of dry processes with regard to fine pattern transfer, HAR feature formation, and multiple  ...  In 2012, Ref. 175 reported 15 nm half-pitch spacers obtained by a combination of EUV lithography and double patterning.  ... 
doi:10.7567/1347-4065/ab1638 fatcat:uangagcsybd6pk4yrlraqhtmdq
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