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Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic

P Balasubramanian, C Dang, D L Maskell, K Prasad
2017 arXiv   pre-print
A new asynchronous early output section-carry based carry lookahead adder (SCBCLA) with alias carry output logic is presented in this paper.  ...  The adders were realized and the simulations were performed based on a 32/28nm CMOS process.  ...  PROPOSED ASYNCHRONOUS EARLY OUTPUT SCBCLA WITHOUT/WITH ALIAS CARRY LOGIC The SCBCLA is based on the concept of dividing an n-bit binary adder into k sub-adder sections (i.e. k sub-SCBCLA modules) where  ... 
arXiv:1710.05470v1 fatcat:pgo2ld5bw5acpin2mdk7jhg22q

Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder [article]

P. Balasubramanian, D.L. Maskell, N.E. Mastorakis
2019 arXiv   pre-print
The cycle time (CT), which is the sum of forward and reverse latencies, governs the speed; and the product of average power dissipation and cycle time viz. the power-cycle time product (PCTP) defines the  ...  Compared to existing asynchronous adders corresponding to various architectures such as ripple carry adder (RCA), conventional carry lookahead adder (CCLA), carry select adder (CSLA), BCLARC, and hybrid  ...  Toms, “Self-timed section-carry based carry lookahead adders and the concept of alias logic,” Journal Circuits, Systems, and Computers, vol. 22, no. 4, pp. 1350028-1 – 1350028-24, April 2013. 33  ... 
arXiv:1903.09433v1 fatcat:5vswc63rb5hzrmqlea23hxxubu

Parameterized Design: Principle [chapter]

2006 RTL Hardware Design Using VHDL  
cell-base carry-ripple multiplier of List- ing 15.19. 15.14 Repeat Problem 15.11, but modify the cell-base carry-save multiplier of List- ing 15.20. 15.15 Both the adder-based multiplier of Section  ...  Cell-based carry-ripple combinational multiplier The previous adder-based multiplier utilizes "coarse" RT-level parts, namely the 2N-bit adders.  ...  The conceptual block diagram and a representative timing diagram are shown in Figure 16 .20.  ... 
doi:10.1002/0471786411.ch14 fatcat:3m4tsvxxd5awve3snrdg7rz5oa

Design of large polyphase filters in the Quadratic Residue Number System

Gian Carlo Cardarilli, Alberto Nannarelli, Yann Oster, Massimo Petricca, Marco Re
2010 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers  
The rather surprising result is that ripple carry adders are faster in QCA than carry lookahead and conditional sum adders.  ...  An overview of implementations of adders, multipliers and dividers is provided. Ripple carry, carry lookahead and conditional sum adder designs are compared.  ... 
doi:10.1109/acssc.2010.5757589 fatcat:ccxnu5owr5fyrcjcqukumerueq

Dependable embedded systems

2008 2008 6th IEEE International Conference on Industrial Informatics  
Titles in the Series cover a focused set of embedded topics relating to traditional computing devices as well as hightech appliances used in newer, personal devices, and related topics.  ...  The material will vary by topic but in general most volumes will include fundamental material (when appropriate), methods, designs and techniques. More information about this series at  ...  We would like to thank Arun Subramaniyan, Duo Sun and Segnon Jean Bruno Ahandagbe for their contributions to parts of the works cited in this chapter.  ... 
doi:10.1109/indin.2008.4618103 fatcat:hal6brsgsjg5rlo3u5xil46pxi

CAS - CERN Accelerator School: Course on Digital Signal Processing [article]

D Brandt
of the participants who came from more than 23 different countries around the world was convincing proof of the usefulness and success of the course.  ...  The specific aim of the course was to introduce the participants to the use and programming of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs) evaluation boards.  ...  participating in the LHC powering and in particular the members of the Power Converter Group, as well as of our partners in industry.  ... 
doi:10.5170/cern-2008-003 fatcat:gz42zmfggffgngh53pkbeqthua