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Multistage Network With Globally Controlled Switching Stages and Its Implementation Using Optical Multi-Interconnection Modules

A. Cassinelli, M. Naruse, M. Ishikawa
2004 Journal of Lightwave Technology  
Plane-to-plane guided-wave-based interconnection modules are proposed as building blocks for scalable optoelectronic multistage interconnection networks (MINs).  ...  Transparent circuit switching for permutation routing is possible in such an unbuffered "globally-switched" multi-stage interconnection network (GSMIN).  ...  We will consider as a starting point the class of self-routed, digitally controlled Delta networks, which covers a very large set of multistage interconnection networks, including the well-known shuffle-exchange  ... 
doi:10.1109/jlt.2004.824385 fatcat:tktmifel4nffji3xwyzbx4vc4y

Performance evaluation of Butterfly on-Chip Network for MPSoCs

Mohammad Arjomand, Hamid Sarbazi-Azad
2008 2008 International SoC Design Conference  
The most MPSoC design challenges are due to infrastructure interconnect. Network-on-Chip (NoC) with multiple constraints to be satisfied is a promising solution for these challenges.  ...  In this paper, we evaluate Butterfly network with arbitrary extra stages as MPSoC infrastructure. Different routing and switching strategies are used for architectural consideration.  ...  The Routing in delta networks is deterministic and distributed Self Routing Algorithm.  ... 
doi:10.1109/socdc.2008.4815631 fatcat:zlxshmmbu5chtlmdhe2k3heimy

Comment: Behaviour of circuit-switched multistage networks in presence of memory hot spot

T.-H. Lee
1990 Electronics Letters  
switched multistage interconnection networks (MINs) in the presence of a memory hot spot.'  ...  A.: "'Hot spot" contention and combining in multistage interconnection networks', IEEE Trans.  ... 
doi:10.1049/el:19900355 fatcat:4uey3awulfac7o7nxyhc5gw3qi

Deterministic versus Adaptive Routing in Fat-Trees

C. Gomez, F. Gilabert, M.E. Gomez, P. Lopez, J. Duato
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
We exploit this idea to propose a deterministic routing algorithm for fat-trees, comparing it with adaptive routing in several workloads.  ...  These machines use commodity PCs linked by a high speed interconnect. Routing is one of the most important design issues of interconnection networks.  ...  Either regular direct networks (tori and meshes) or indirect multistage networks (MINs) are the usual choice.  ... 
doi:10.1109/ipdps.2007.370482 dblp:conf/ipps/GomezGGLD07 fatcat:gyvwetxjy5h6xpizr6bp42oqou

Area-efficient architectures for the Viterbi algorithm. I. Theory

C.B. Shung, H.-D. Lin, R. Cypher, P.H. Siegel, H.K. Thapar
1993 IEEE Transactions on Communications  
The area saving of our architecture comes from the reduced number of both the ACS's and interconnection wires. The design of the ACS, path metric storage, and routing network is discussed in detail.  ...  Paper approved by the Editor for VLSI in Communications of the IEEE Communications Society.  ...  Hwang for many helpful discussions.  ... 
doi:10.1109/26.223789 fatcat:rscphva2pvgqzkblflsgsuvcqa

The Folded Hypercube ATM Switches [chapter]

Jahng S. Park, Nathaniel J. Davis
2001 Lecture Notes in Computer Science  
To guarantee faster switching of time-sensitive cells, the routing algorithm of the three switches uses a priority scheme that gives higher precedence to the time-sensitive cells.  ...  Therefore, there is a need for switch designs with low complexity and high performance. This research proposes three new ATM switches based on the folded hypercube network (FHC).  ...  (or multistage interconnection networks).  ... 
doi:10.1007/3-540-47734-9_37 fatcat:7pnxi33dcrbvflwpabbxopspbq

Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System

Javier Navaridas, Mikel Luj'n, Luis A. Plana, Jose Miguel-Alonso, Steve B. Furber
2012 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems  
Finally, we derived the amount of neurons the different networks can support.  ...  This paper shows analytical proof that the novel multicast router in SpiNNaker is a better solution for simulating neural nets than more powerful point-to-point routers such as those found on datacentres  ...  For the sake of completeness we also show N m , the empirical average network utilization of 10 5 random runs using a simple multicast route generation algorithm.  ... 
doi:10.1109/hpcc.2012.11 dblp:conf/hpcc/NavaridasLPMF12 fatcat:jcmk7wgjrvffpmf5fv4wraqrrm

Grain-size considerations for optoelectronic multistage interconnection networks

Ashok V. Krishnamoorthy, Philippe J. Marchand, Fouad E. Kiamilev, Sadik C. Esener
1992 Applied Optics  
The specific system considered is a packet-switched, free-space optoelectronic shuffle-exchange multistage interconnection network (MIN).  ...  A detailed design and analysis of a two-dimensional (2-D) optoelectronic shuffle-exchange routing network with variable grain size K is presented.  ...  Review of Multistage Interconnection Network Architectures The basic building block of a MIN is a K x K self-contained switching element.  ... 
doi:10.1364/ao.31.005480 pmid:20733733 fatcat:2ehey7kqibgt7hxskcc6fzvqem

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Fateh Boutekkouk
2018 International Journal of Recent Contributions from Engineering, Science & IT  
Network-On-Chip (NOC) is an emerging paradigm to surmount traditional bus based Systems-On-Chip (SOC) limits especially scalability and communication performances.  ...  A Clos network is a kind of multistage circuit switching network used in the field of telecommunications.  ...  They formalized multistage interconnection networks with semantics inspired by the high-level version of the Petri box algebra, which allows one to represent concurrent communication systems in a compositional  ... 
doi:10.3991/ijes.v6i4.9416 fatcat:7fljmcayfvdgpd7v3d4vt7lkvu

Array Organization in Parallel Memories

Mayez Al-Mouhamed
2004 International journal of parallel programming  
An effective compiler heuristic is proposed for finding a the storage matrix that minimizes overall memory access time. This applies to arbitrary linear patterns and arbitrary alignment networks.  ...  The performance and scalability of the proposed parallel memory and its predictable access time are presented using numerical and multimedia algorithms.  ...  can perform for arbitrary multistage network.  ... 
doi:10.1023/b:ijpp.0000023481.20270.d3 fatcat:pmwag2civffsrkknx4eibeeefm

Emerging Technologies and Nanoscale Computing Fabrics [chapter]

Ian O'Connor, Junchen Liu, Jabeur Kotb, Nataliya Yakymets, Renaud Daviot, David Navarro, Pierre-Emmanuel Gaillardon, Fabien Clermidy, Maïmouna Amadou, Gabriela Nicolescu
2011 IFIP Advances in Information and Communication Technology  
This chapter describes a reconfigurable computing architecture based on clusters of regular matrices of fine-grain dynamically reconfigurable cells using double-gate carbon nanotube field effect transistors  ...  This work shows how circuit and architecture designers can work with emerging technology concepts to examine its suitability for use in computing platforms.  ...  While the application is quite close to logic synthesis and network routing, the fact that we have introduced computing inside the matrix means that we cannot use routing algorithms or synthesis algorithms  ... 
doi:10.1007/978-3-642-23120-9_1 fatcat:lhmx45k2vrdzvcm6nxqrapflwy

Reference list of indexed articles

2000 Discrete Applied Mathematics  
Hollmann and J.H. van Lint, Nonblocking self-routing switching networks 37/38 (1992) 3 19-340 923. X.D. Hu and F.K.  ...  Jean-Marie, A graph theoretical approach to equivalence of multistage interconnection networks 22 (1988/89) 201-214 591. T.J. Marlowe and M.C.  ... 
doi:10.1016/s0166-218x(00)00209-2 fatcat:l53yxlj45ffdrdecl3uah2gj3y

Emerging technologies and nanoscale computing fabrics

Ian O'Connor
2009 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)  
While the application is quite close to logic synthesis and network routing, the fact that we have introduced computing inside the matrix means that we cannot use routing algorithms or synthesis algorithms  ...  In fact, Multistage Interconnection Networks (MIN) are designed to interconnect layers in an efficient way and can be applied in this context.  ... 
doi:10.1109/vlsisoc.2009.6041320 fatcat:xcotcekxwfho5abh6ydylfc564

Designing Chip-Level Nanophotonic Interconnection Networks [chapter]

Christopher Batten, Ajay Joshi, Vladimir Stojanovć, Krste Asanović
2012 Integrated Optical Interconnect Architectures for Embedded Systems  
There have been many recent proposals for nanophotonic interconnection networks that attempt to provide improved performance and energy-ef fi ciency compared to electrical networks.  ...  This chapter discusses the approach we have used when designing such networks, and provides a foundation for designing new networks.  ...  We would like to thank our co-authors on the various publications that served as the basis for the three case studies, including Y.  ... 
doi:10.1007/978-1-4419-6193-8_3 fatcat:rqyqnccg4nhx5lwiabju5d3dwa

Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems

Luca Ramini, Herve Tatenguem Fankem, Alberto Ghiribaldi, Paolo Grani, Marta Ortin-Obon, Anja Boos, Sandro Bartolini
2014 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)  
This concern is especially critical for wavelength-routed ONoCs, which fundamentally consist of add-drop optical filters, and therefore end up in multistage interconnection networks that map inefficiently  ...  Due to the complexity of the placement and routing problem our algorithm Manual Design vs.  ... 
doi:10.1109/nocs.2014.7008778 dblp:conf/nocs/RaminiFGGOBB14 fatcat:rfhirddgcrflld2hjkb24ajzti
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