Filters








380 Hits in 5.5 sec

Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier

Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel Sorin
2006 Test Conference (ITC), Proceedings, IEEE International  
Our fault tolerant multiplier designs are capable of detecting and correcting errors, diagnosing hard faults, and reconfiguring to take the faulty subunit off-line.  ...  In this paper, we propose a low-cost fault tolerance technique for microprocessor multipliers, both non-pipelined (NP) and pipelined (P).  ...  In this paper, we present a recursive, fault tolerant 32-bit multiplier in the context of modern microprocessors.  ... 
doi:10.1109/test.2006.297634 dblp:conf/itc/YilmazHOS06 fatcat:zto6fzgjrbebtjpjjlkw27fgvu

Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor

Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz
2007 2007 25th International Conference on Computer Design  
Results show that we can diagnose all injected delay faults and that prior diagnosis mechanisms, which target only stuck-at faults, miss the majority of them.  ...  Our goal is to diagnose hard delay faults (i.e., identify them as hard faults, not transients) during run-time before they lead to catastrophic chip failures.  ...  Table 3 summarizes the overhead results for our implementation of the 32-bit integer adder and the 32-bit multiplier.  ... 
doi:10.1109/iccd.2007.4601919 dblp:conf/iccd/OzevSY07 fatcat:tkjargm7jjgrles36k7fcvcjqm

Tolerating hard faults in microprocessor array structures

F.A. Bower, P.G. Shealy, S. Ozev, D.J. Sorin
2004 International Conference on Dependable Systems and Networks, 2004  
In this paper, we present a hardware technique, called Self-Repairing Array Structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buffer and branch history  ...  To detect row errors, every write to a row is mirrored to a dedicated "check row." We then read out both the written row and check row and compare their results.  ...  Acknowledgments This work is supported in part by the National Science Foundation, under grants CCR-0309164 and EIA-9972879, IBM, and a Duke Warren Faculty Scholarship.  ... 
doi:10.1109/dsn.2004.1311876 dblp:conf/dsn/BowerSOS04 fatcat:ydaplifaczbmdopusej4lthqg4

Ultra low-cost defect protection for microprocessor pipelines

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin
2006 SIGARCH Computer Architecture News  
In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects.  ...  Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity  ...  Acknowledgments This work is supported by grants from NSF and the Gigascale Systems Research Center.  ... 
doi:10.1145/1168919.1168868 fatcat:735im5zajzbpxcsyijynplvdwq

Ultra low-cost defect protection for microprocessor pipelines

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin
2006 SIGPLAN notices  
In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects.  ...  Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity  ...  Acknowledgments This work is supported by grants from NSF and the Gigascale Systems Research Center.  ... 
doi:10.1145/1168918.1168868 fatcat:kqpadu2enzhhpihpxbztyvw73q

Ultra low-cost defect protection for microprocessor pipelines

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin
2006 Proceedings of the 12th international conference on Architectural support for programming languages and operating systems - ASPLOS-XII  
In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects.  ...  Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity  ...  Acknowledgments This work is supported by grants from NSF and the Gigascale Systems Research Center.  ... 
doi:10.1145/1168857.1168868 dblp:conf/asplos/ShyamCPBA06 fatcat:hcqq4pai5ngjni6rbi4nukad3m

Ultra low-cost defect protection for microprocessor pipelines

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin
2006 ACM SIGOPS Operating Systems Review  
In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects.  ...  Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity  ...  Acknowledgments This work is supported by grants from NSF and the Gigascale Systems Research Center.  ... 
doi:10.1145/1168917.1168868 fatcat:6nm2os5525aapmbhgxhg3ceopi

Online diagnosis of hard faults in microprocessors

Fred A. Bower, Daniel J. Sorin, Sule Ozev
2007 ACM Transactions on Architecture and Code Optimization (TACO)  
Experimental results show that our reliable microprocessor quickly and accurately diagnoses each hard fault that is injected and continues to function, albeit with somewhat degraded performance.  ...  We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy.  ...  ACKNOWLEDGMENTS We thank Alvy Lebeck and the rest of the Duke Architecture Reading Group for helpful feedback on this paper.  ... 
doi:10.1145/1250727.1250728 fatcat:lq2g3lffebaatixrm7rmycqdbe

PMUX - The interface for engine data to AIDS

J. A. BLUISH, W. LORENZ
1983 Journal of Guidance Control and Dynamics  
CPU and memory self-test capability includes periodic checks of CPU operation, data retention, and system timing.  ...  Failures there must be detected by input range and rate checks. The PMUX (EAROM) memory is also helpful in diagnosing engine, engine sensor, and PMUX signal processing problems.  ... 
doi:10.2514/3.19807 fatcat:mlobvdyge5fbbmvxdahup66dia

SoftBeam: Precise tracking of transient faults and vulnerability analysis at processor design time

Michael Gschwind, Valentina Salapura, Catherine Trammell, Sally A. McKee
2011 2011 IEEE 29th International Conference on Computer Design (ICCD)  
We use soft error injection into randomly selected latch bits to (1) identify areas for improvement, (2) derate technology susceptibility by architectural, microarchitectural, and logic masking resulting  ...  Based on these results, we reduce design vulnerability to soft errors by factors ranging from 2 for an execution unit to more than 32 for a memory management unit.  ...  error injection with Fusion and the FLite environment, and with model build.  ... 
doi:10.1109/iccd.2011.6081430 dblp:conf/iccd/GschwindSTM11 fatcat:dw7ovpsfwfbxvkejh6cso4tpc4

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores

Albert Meixner, Michael E. Bauer, Daniel Sorin
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
The key to Argus is that the operation of a von Neumann core consists of four fundamental tasks-control flow, dataflow, computation, and memory access-that can be checked separately.  ...  Experiments show that Argus-1 detects transient and permanent errors in simple cores with much lower impact on performance (<4% average overhead) and chip area (<17% overhead) than previous techniques.  ...  We thank Fred Bower, Derek Hower, Alvy Lebeck, Anita Lungu, and Bogdan Romanescu for feedback on this work. We thank Bogdan Romanescu and Heather Sarik for help with the experiments.  ... 
doi:10.1109/micro.2007.4408257 fatcat:fh4t4wiz45cizlkvq53dsyqeqy

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores

Albert Meixner, Michael E. Bauer, Daniel Sorin
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
The key to Argus is that the operation of a von Neumann core consists of four fundamental tasks-control flow, dataflow, computation, and memory access-that can be checked separately.  ...  Experiments show that Argus-1 detects transient and permanent errors in simple cores with much lower impact on performance (<4% average overhead) and chip area (<17% overhead) than previous techniques.  ...  We thank Fred Bower, Derek Hower, Alvy Lebeck, Anita Lungu, and Bogdan Romanescu for feedback on this work. We thank Bogdan Romanescu and Heather Sarik for help with the experiments.  ... 
doi:10.1109/micro.2007.18 dblp:conf/micro/MeixnerBS07 fatcat:g74a6zasczcw3jk4bmwwhrdouy

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores

Albert Meixner, Michael E. Bauer, Daniel J. Sorin
2008 IEEE Micro  
The key to Argus is that the operation of a von Neumann core consists of four fundamental tasks-control flow, dataflow, computation, and memory access-that can be checked separately.  ...  Experiments show that Argus-1 detects transient and permanent errors in simple cores with much lower impact on performance (<4% average overhead) and chip area (<17% overhead) than previous techniques.  ...  We thank Fred Bower, Derek Hower, Alvy Lebeck, Anita Lungu, and Bogdan Romanescu for feedback on this work. We thank Bogdan Romanescu and Heather Sarik for help with the experiments.  ... 
doi:10.1109/mm.2008.3 fatcat:5wkl4zbvgbhhja3arzpdow44zi

Signature Analyzer Design for Yield Learning Support

Nishant Patil, Subhasish Mitra, Steven Lumetta
2006 Test Conference (ITC), Proceedings, IEEE International  
The signature analyzers described also tolerate unknown logic values (X's) and are useful for Built-In-Self-Test and test compression with yield analysis support.  ...  Depending on the desired accuracy of failing response bit identification and the number of X's, test response data is reduced by up to two orders of magnitude.  ...  Subhasish Mitra and Steve Lumetta were also supported in part by grants from the DARPA/MARCO Gigascale Systems Research Center.  ... 
doi:10.1109/test.2006.297719 dblp:conf/itc/PatilML06 fatcat:yyilncvrtzbe7o3nie6uurnq4y

Subframe multiplexing for FPGA manufacturing test configuration

Erik Chmelar
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
This design for test technique requires only a minor modification to the existing configuration hardware---the addition of several two-bit multiplexers---while maintaining the same configuration memory  ...  The place and route tool can be used to systematically explore alternative place and route strategies and was used to obtain significantly better area utilization and timing performance compared to general-purpose  ...  This paper proposes a bit-level super-systolic FIR filter with a FPGA-based bit-serial semi-systolic multiplier.  ... 
doi:10.1145/968280.968315 dblp:conf/fpga/Chmelar04 fatcat:bkkwooxvszbvlfrg4b7h5svtvi
« Previous Showing results 1 — 15 out of 380 results