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Implementing Intrusion Detection System for Multicore Processor

Rajeswari G., Nithya B.
2009 2009 International Conference on Advances in Recent Technologies in Communication and Computing  
Multi-core processors represent a major evolution in computing hardware technology. Multi-core provides a network security application with more processing power from the hardware perspective.  ...  The Intrusion Detection System that we Presented in this paper also protect the multi core systems from Real Time attacks and Packet Filtrations with high performance without any penalty.  ...  The information from packets, events, flows, and messages are processed in the multi-core processor in parallel. The processor has spare cores to run other applications.  ... 
doi:10.1109/artcom.2009.44 dblp:conf/artcom/RajeswariN09 fatcat:nbc6yirovvhizidphczu22e7ay

A Novel Header Matching Algorithm For Intrusion Detection Systems

Mohammad A Alia, Adnan A Hnaif, Hayam K Al Anie, Khulood Abu Maria, Ahmed M Manasrah, M Imran Sarwar
2011 International journal of network security and its applications  
This algorithm can be run on a single processor or multiple-cores platform.  ...  Therefore, the main objective of this paper is to enhance the speed of engine detection in real time for packet header in NIDS.  ...  The Multi-Processors Technology The authors of (Li, J. Y. 2005) used a multi-processor technology to parallelize the AC algorithm.  ... 
doi:10.5121/ijnsa.2011.3406 fatcat:si6hx7jxwncf3mlhky7viyktqi

Design and Evaluation of Parallel String Matching Algorithms for Network Intrusion Detection Systems [chapter]

Tyrone Tai-On Kwok, Yu-Kwong Kwok
2007 Lecture Notes in Computer Science  
Experimental results show that, on a multi-processor system, the multi-threaded implementation of the proposed parallel string matching algorithm can reduce string matching time by more than 40%.  ...  In this paper, we present the design and evaluation of parallel string matching algorithms targeting hardware implementation on FPGAs and software implementation on multi-core processors.  ...  To mitigate this problem, we develop a multi-threaded version of CAMP (MT-CAMP) for implementation on a multi-core-processor-based system.  ... 
doi:10.1007/978-3-540-74784-0_35 fatcat:2epumeo3ovab5n4hmrnxotl46e

Multi-core Implementation of Decomposition-Based Packet Classification Algorithms [chapter]

Shijie Zhou, Yun R. Qu, Viktor K. Prasanna
2013 Lecture Notes in Computer Science  
This paper presents four decomposition-based approaches on multi-core processors.  ...  Multi-field packet classification is a network kernel function where packets are classified based on a set of predefined rules.  ...  (b) Latency on the Intel processor Figure 6 . 6 Breakdown of the latency per packet on (a) the AMD multi-core processor and (b) the Intel multi-core processors (1K rule set, 5 threads per core) Figure  ... 
doi:10.1007/978-3-642-39958-9_9 fatcat:2b6l52wlrvaprgtfpu3yk6ysde

High-performance multi/many-core network processing architectures with shared and private queues

Reza Falamarzi, Bahram Bahrambeigy, Mahmood Ahmadi, Amir Rajabzade
2015 2015 7th Conference on Information and Knowledge Technology (IKT)  
In this paper, two schemes called multi-core architecture with shared queue and multi-core architecture with private queue (both employing Bloom filter cores) are proposed and implemented on FPGA.  ...  The inherent parallelism in querying of packets and different number of cores (such as 1, 2, 4, 8 and 16 cores) are considered.  ...  Their method is implemented on a platform of 16 MIPS cores. In [10] , a method is presented for packet classification which is optimized for multi-core network processors.  ... 
doi:10.1109/ikt.2015.7288757 fatcat:ysrslf2fa5a7fbx6nj62eydevu

Implementation of Cache Fair Thread Scheduling for multi core processors using wait free data structures in cloud computing applications

A.S. Radhamani, E. Baburaj
2011 2011 World Congress on Information and Communication Technologies  
As multi-core processors with tens or hundreds of cores begin to grow, system optimization issues once faced only by the High-Performance Computing (HPC).  ...  To satisfy the requirement, one can leverage multi-core architectures to parallelize traffic monitoring so as to progress information processing capabilities over traditional uni-processor architectures  ...  This may happen when two threads using the same data set are scheduled on different processors, or on the same multi-core processors having separate cache domains.  ... 
doi:10.1109/wict.2011.6141313 fatcat:awglbzxx3bay3fn5d7atbof3lm

SURVEY ON SIGNATURE BASED INTRUCTION DETECTION SYSTEM USING MULTITHREADING

Sanjay Roka, Santosh Naik
2017 International journal of research - granthaalayah  
A multi-threaded technique would allow more efficient and scalable exploitation of these multi-processor machines.  ...  Current implementations of IDS employ only a single thread of execution and as a consequence benefit very little from multi-processor hardware platforms.  ...  Multi-threading is a single core or multi-core processor's ability to execute multiple threads at the same time.  ... 
doi:10.29121/granthaalayah.v5.i4racsit.2017.3352 fatcat:wm7xawa23zhkrl3qztg4ey7qam

Real-time pre-processing system with hardware accelerator for mobile core networks

Mian Cheng, Jin-shu Su, Jing Xu
2017 Frontiers of Information Technology & Electronic Engineering  
In this paper, we design and evaluate a real-time pre-processing system, which includes a hardware accelerator and a multi-core processor.  ...  Network probing tools, which are deployed as a bypass device at a mobile core network gateway, can collect and analyze all the traffic for security detection.  ...  the hardware accelerator and multi-core processor.  ... 
doi:10.1631/fitee.1700507 fatcat:jon36m46nfhnbb7eml6ruvfkty

Data Packet Processing Model based on Multi-Core Architecture

Xian Zhang
2018 International Journal of Performability Engineering  
According to the characteristics of pipeline structure and multi-core processor structure for packet processing in network detection applications, the horizontal-based parallel architecture model and tree-based  ...  The principle of a tree-based parallel architecture model is to use pipelining and flow-pinning technology to design a processor that is specifically used to capture data packets, and other processors  ...  Every processor core thread runs the same packet pipelining process for network intrusion detection application Snort.  ... 
doi:10.23940/ijpe.18.07.p1.13831390 fatcat:4flik2anyjf2bjaomndflc3che

An architecture for exploiting multi-core processors to parallelize network intrusion prevention

Vern Paxson, Robin Sommer
2007 2007 IEEE Sarnoff Symposium  
Taking advantage of the full power of multi-core processors requires a more in-depth approach.  ...  Taking advantage of the full power of multi-core processors for network intrusion prevention requires an in-depth approach.  ...  Of particular note is the large degree of task-level parallelism, which can easily be leveraged by multi-core and multi-threaded processors.  ... 
doi:10.1109/sarnof.2007.4567341 fatcat:5e3n2zwfbbdrjkpnvcwloxsa6m

An architecture for exploiting multi-core processors to parallelize network intrusion prevention

Robin Sommer, Vern Paxson, Nicholas Weaver
2009 Concurrency and Computation  
Taking advantage of the full power of multi-core processors requires a more in-depth approach.  ...  Taking advantage of the full power of multi-core processors for network intrusion prevention requires an in-depth approach.  ...  Of particular note is the large degree of task-level parallelism, which can easily be leveraged by multi-core and multi-threaded processors.  ... 
doi:10.1002/cpe.1422 fatcat:7yq5tk4n2neenmtbpr5jnkeatq

Fast Path Session Creation on Network Processors

Bo Xu, Yaxuan Qi, Fei He, Zongwei Zhou, Yibo Xue, Jun Li
2008 2008 The 28th International Conference on Distributed Computing Systems  
The security gateways today are required not only to block unauthorized accesses by authenticating packet headers, but also by inspecting connection states to defend against malicious intrusions.  ...  In this paper, we propose a high-speed session creation scheme optimized for network processors.  ...  The authors also would like to acknowledge the colleagues in Network Security Lab for their suggestions.  ... 
doi:10.1109/icdcs.2008.33 dblp:conf/icdcs/XuQHZXL08 fatcat:cdyizx6minh5boew3e7nwrxlm4

Towards High-Performance Network Intrusion Prevention System on Multi-core Network Services Processor

Xiang Wang, Yaxuan Qi, Baohua Yang, Yibo Xue, Jun Li
2009 2009 15th International Conference on Parallel and Distributed Systems  
Performance evaluation shows that, our prototype NIPS on Cavium OCTEON3860 processor can reach line-rate stateful inspection and multi-Gbps deep inspection performance.  ...  and flexible pipeline and parallel processing, flow-level packet-order preserving, and latency hiding of deep packet inspection.  ...  With the recent advance in technology, the industry extends the NP concept and proposes a newly designed multi-core network processor with security and application hardware acceleration engines, Network  ... 
doi:10.1109/icpads.2009.109 dblp:conf/icpads/WangQYXL09 fatcat:sxzyawtq35bezb67j3tsvia7fa

Harnessing Multicore Processors for High-Speed Secure Transfer

John Bresnahan, Rajkumar Kettimuthu, Mike Link, Ian Foster
2007 2007 High-Speed Networks Workshop  
We expect that multi-core processors would become more common than SSL/IPSec offload engines.  ...  Further, we would like to utilize the parallel and higher processing power that the multi-core technology promises to achieve high-speed secure data transfers.  ...  We expect that multi-core processors would become more common than SSL/IPSec offload engines.  ... 
doi:10.1109/hsnw.2007.4290546 fatcat:hlvmnqn7hzdynceairmdmchkqq

Transparent multi-core cryptographic support on Niagara CMT Processors

James Hughes, Gary Morton, Jan Pechanec, Christoph Schuba, Lawrence Spracklen, Bhargava Yenduri
2009 2009 ICSE Workshop on Multicore Software Engineering  
We explore this question in the context of the Ultra-SPARC T1 and T2 processor family, Chip Multi-Threaded (CMT) processors that have hardware cryptographic accelerators integrated on-chip with 8-core  ...  While the inclusion of cryptographic accelerator functionality in the processor chip is not new, this paper investigates the question of how to transparently combine such multi-core cryptographic processor  ...  The UltraSPARC cryptographic accelerators Starting with the introduction of Sun's UltraSPARC T1 processor in 2004, Sun's Chip Multi-Threaded (CMT) processors (see [9] ) have had hardware cryptographic  ... 
doi:10.1109/iwmse.2009.5071387 fatcat:yxrotctdkfesnkzi7hgqqyzpli
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