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Secure scan: a design-for-test architecture for crypto chips

Bo Yang, Kaijie Wu, R. Karri
2005 Proceedings. 42nd Design Automation Conference, 2005.  
Scan-based Design-for-Test (DFT) is a powerful testing scheme, but it can be used to retrieve the secrets stored in a crypto chip thus compromising its security.  ...  Based on this key observation, we propose a novel scan DFT architecture called secure scan that maintains the high test quality of traditional scan DFT without compromising the security.  ...  The design goal for the secure scan DFT architecture is two folds: • Crypto chips should be tested and debugged using general scan-based DFT. • Information obtained from scan chains cannot be used to retrieve  ... 
doi:10.1109/dac.2005.193787 fatcat:rxs6mccfbrg3jbhuz3gobuawje

Secure Scan: A Design-for-Test Architecture for Crypto Chips

B. Yang, K. Wu, R. Karri
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Scan-based Design-for-Test (DFT) is a powerful testing scheme, but it can be used to retrieve the secrets stored in a crypto chip thus compromising its security.  ...  Based on this key observation, we propose a novel scan DFT architecture called secure scan that maintains the high test quality of traditional scan DFT without compromising the security.  ...  The design goal for the secure scan DFT architecture is two folds: • Crypto chips should be tested and debugged using general scan-based DFT. • Information obtained from scan chains cannot be used to retrieve  ... 
doi:10.1109/tcad.2005.862745 fatcat:w6sqnz3sxff3vpzol66vqha4da

Secure scan

Bo Yang, Kaijie Wu, Ramesh Karri
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
Scan-based Design-for-Test (DFT) is a powerful testing scheme, but it can be used to retrieve the secrets stored in a crypto chip thus compromising its security.  ...  Based on this key observation, we propose a novel scan DFT architecture called secure scan that maintains the high test quality of traditional scan DFT without compromising the security.  ...  The design goal for the secure scan DFT architecture is two folds: • Crypto chips should be tested and debugged using general scan-based DFT. • Information obtained from scan chains cannot be used to retrieve  ... 
doi:10.1145/1065579.1065617 dblp:conf/dac/YangWK05 fatcat:wcrrz7mosjbeppxsevdbep3ine

Analysis of Recent Secure Scan Test Techniques

Cheng Xing, Sungju Park, Ji Zhao
2016 Journal of Software Engineering and Applications  
Side channel attack may result in user key leakage as scan test techniques are applied for cryptographic chips. Many secure scan designs have been proposed to protect the user key.  ...  This paper meticulously selects three current scan test techniques, analyses their advantages and disadvantages and also compares them in security and area overhead.  ...  Conclusion This thesis discusses three recent secure DFT techniques for crypto core.  ... 
doi:10.4236/jsea.2016.93008 fatcat:qlpum7uhqvbnbnu5d2pob4rx54

Analysis of recent secure scan test techniques

Xing Cheng, Sungju Park
2016 2016 Chinese Control and Decision Conference (CCDC)  
Side channel attack may result in user key leakage as scan test techniques are applied for cryptographic chips. Many secure scan designs have been proposed to protect the user key.  ...  This paper meticulously selects three current scan test techniques, analyses their advantages and disadvantages and also compares them in security and area overhead.  ...  Conclusion This thesis discusses three recent secure DFT techniques for crypto core.  ... 
doi:10.1109/ccdc.2016.7532082 fatcat:eelphb3aibatrmrmglpj46otei

Vulnerability modelling of crypto-chips against scan-based attacks

Mohammad Taherifard, Ahmad Patooghy, Mahdi Fazeli
2018 IET Information Security  
In this study, a gate-level vulnerability model is proposed to detect the potential security holes of crypto-chips against scan-based attacks.  ...  The proposed model offers a relative measure so-called vulnerability factor (VF) for each net of a given crypto-chip.  ...  Scan chain architecture is originally designed to ease the structural test of digital circuits.  ... 
doi:10.1049/iet-ifs.2017.0440 fatcat:aoh227it6jarxfd5t76bjk3wdq

Rectifying Various Scan-based Attacks on Secure IC'S

C. Ramya, S. Saravanan
2015 Indian Journal of Science and Technology  
The proposed method can be applied for all scan testing.  ...  From the security point of view, few limitations of existing method limit the security level. Some countermeasures have been proposed in order to secure the scan technique and on-chip comparison.  ...  The new method can be implemented after the synthesis of DUT and achieves high security against the scan attacks with proper protection. References  ... 
doi:10.17485/ijst/2015/v8i13/61856 fatcat:yzz726c355gt5mjfzzooetazyq

Scan-Based Attack Tolerance with Minimum Testability Loss: A Gate-Level Approach

Mohammad Taherifard, Mahdi Fazeli, Ahmad Patooghy
2020 IET Information Security  
Scan chain is an architectural solution to facilitate in-field tests and debugging of digital chips, however, it is also known as a source of security problems, e.g. scan-based attacks in the chips.  ...  The authors conduct a comprehensive gate-level security analysis on crypto-chips, which are equipped with a scan chain, and then propose a set of protection mechanisms to immune vulnerable nets of the  ...  However, a major challenge for scan chain enabled crypto-chips is how to establish a trade-off between testability and security.  ... 
doi:10.1049/iet-ifs.2019.0444 fatcat:5b53w35wqjc3tflloqpmvdc42u

A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key

Hyungil Woo, Seokjun Jang, Sungho Kang
2021 IEEE Access  
In this paper, we propose a secure scan architecture using a skew-based lock and key to enhance the security of the scan design while maintaining the debuggability of the scan dump.  ...  However, scan-based DFT is prone to security vulnerabilities where attackers use the scan design to obtain secret information from the system-on-chip.  ...  INTRODUCTION Scan architecture is a common and dominant Design for Testability (DFT) methodology in modern systemon-chip (SOC) devices as it is beneficial for obtaining high test coverage [1] .  ... 
doi:10.1109/access.2021.3097348 fatcat:nhducotmbbfy3dtzoqikqehwga

A hardware security solution against scan-based attacks

Ankit Mehta, Darius Saif, Rashid Rashidzadeh
2016 2016 IEEE International Symposium on Circuits and Systems (ISCAS)  
In [89] [90] , various secure scan based designs for test are discussed and a secure design for a test technique is proposed by using a popular hash function called CRC-MAC (cyclic redundancy check-message  ...  The authors have implemented the CRC-MAC algorithm to have a secure design for a test solution.  ... 
doi:10.1109/iscas.2016.7538894 dblp:conf/iscas/MehtaSR16 fatcat:vyg6war4xfg57fjezfneaxj7nq

Hardware Security in Case of Scan Based Attack on Crypto Hardware

Jayesh Popat, Usha Mehta
2018 International Journal of VLSI Design & Communication Systems  
The latest innovation technology in computing devices has given a rise of compact, speedy and economical products which also embeds cryptography hardware on-chip.  ...  The attacker may leak secret information from symmetric crypto-hardware (AES, DES etc.) using side-channel analysis, fault injection or exploiting existing test infrastructure.  ...  Virendra Singh for detail review, insightful comments and constructive suggestions.  ... 
doi:10.5121/vlsic.2018.9201 fatcat:l3awhu4juvamnjac63uaysqfpy

Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications

Wang, Deng, Wang, Sangaiah, Cai, Almakhadmeh, Tolba
2019 Sensors  
Nevertheless, scan design provides a backdoor for attackers to deduce the cipher key of a cryptographic core.  ...  The enhanced scan scheme ensures the security of cryptographic chips while remaining the advantages of scan design.  ...  The scan design gives attackers a side-channel to crack a crypto chip.  ... 
doi:10.3390/s19204598 fatcat:yo5bvzdzznebhoaklquogkwe3i

A New Secure Stream Cipher for Scan Chain Encryption

Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
2018 2018 IEEE 3rd International Verification and Security Workshop (IVSW)  
The accessibility to the internal IP cores of Systems on Chip (SoC) provided by the testing infrastructures is a serious security threat.  ...  It has been known for many years that the scan chains can be exploited to retrieve secret keys of cryptoprocessors.  ...  This limitation is therefore not a security concern. V. CONCLUSION Scan chains are a potential threat for circuits embedding a secret, such as crypto-cores.  ... 
doi:10.1109/ivsw.2018.8494852 dblp:conf/ivsw/SilvaVFDNR18 fatcat:ak36iltfnnbsxocusvjjtdyawa

New security threats against chips containing scan chain structures

Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2011 2011 IEEE International Symposium on Hardware-Oriented Security and Trust  
Several scan-based attacks on cryptographic functions have been described and showed the need for secure scan implementations. These attacks assume a single scan chain.  ...  However the conception of large designs and restrictions in terms of test costs may require the implementation of many scan chains and additional test infrastructures for test response compaction.  ...  INTRODUCTION While scan insertion is one of the most popular Design for Testability (DfT) methods, its use for secure devices, smart cards for instance, opens a backdoor for security threats.  ... 
doi:10.1109/hst.2011.5955005 dblp:conf/host/DaRoltNFR11 fatcat:2nmyf7qckjaqji6qeyo2d4b2ba

Scan chain encryption for the test, diagnosis and debug of secure circuits

Mathieu Da Silva, Marie-lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo
2017 2017 22nd IEEE European Test Symposium (ETS)  
Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data, in particular secret keys used in crypto-processors for encoding information in such a way that only knowledge of  ...  This solution does not require additional key management, provides same test/diagnostic and debug facilities as under classical scan design with marginal impacts on area and test time.  ...  Indeed, it is necessary to test the scan ciphers without transforming them into a classical scan design, otherwise the overall security would be jeopardized (the scan attack could be applied on these scan  ... 
doi:10.1109/ets.2017.7968248 dblp:conf/ets/SilvaFNRPR17 fatcat:xfs6kokdh5fd3bff5nungsfak4
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