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SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory

Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja
2020 IEEE Access  
for the ME-AFMRAM compared to other NVMs including STT-MRAM and PCM.  ...  The proposed SMART memory is not only resilient against data confidentiality attacks seeking to leak sensitive information but also ensures data integrity and prevents Denial-of-Service (DoS) attacks on  ...  He is the Director of the Design-for-Excellence Lab, NYU Abu Dhabi. His recent research in hardware security and trust is being funded by the U.S. National Science Foundation, the U.S.  ... 
doi:10.1109/access.2020.2988889 fatcat:53jai2zn4rdyvcrumk6xoospx4

Hardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques [article]

Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao
2020 arXiv   pre-print
Since hardware security has become one of the major concerns in circuit designs, this paper, for the first time, investigates spin-based computing-in-memory (SpinCIM) from a security perspective.  ...  We focus on two fundamental questions: 1) how the new SpinCIM computing paradigm can be exploited to enhance hardware security?  ...  In SpinCIM computing paradigm, the core bit-cell and array structure of STT-MRAM remain unchanged.  ... 
arXiv:2006.01425v1 fatcat:go556fucybhcpld6r7mymvqxru

Emerging Physical Unclonable Functions With Nanotechnology

Yansong Gao, Damith C. Ranasinghe, Said F. Al-Sarawi, Omid Kavehei, Derek Abbott
2016 IEEE Access  
Currently, most PUF designs focus on exploiting process variations intrinsic to CMOS technology.  ...  Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs.  ...  Statistical analysis on trade-offs among uniqueness, randomness, BER, resilience to model building attacks and side-channel attacks, and overhead costs are expected to be taken into consideration for a  ... 
doi:10.1109/access.2015.2503432 fatcat:3x4sayz2draqxbbd6aubrnn4uy

Guest Editorial: Special Section on Emerging Trends and Computing Paradigms for Testing, Reliability and Security in Future VLSI Systems

Stefano Di Carlo, Peilin Song, Alessandro Savino
2021 IEEE Transactions on Emerging Topics in Computing  
security against Power Analysis.  ...  It then demonstrates using Simulation-based Differential Power Analysis significant improvements in security levels in an x25 factor, with negligible degradation in performance.  ... 
doi:10.1109/tetc.2021.3070450 fatcat:afmx7blo55f3tgkizxmqn6mp2i

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

Mohammad Nasim Imtiaz Khan, Swaroop Ghosh
2021 Journal of Low Power Electronics and Applications  
They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues.  ...  This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications.  ...  In [84] , a differential power analysis (DPA) on STTRAM read/write operation and MRAM read operation is performed. The work used the HD model with Pearson correlation.  ... 
doi:10.3390/jlpea11040036 fatcat:jq3tc4ianzd2tmjn6gulb7tmdq

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories [article]

Mohammad Nasim Imtiaz Khan, Swaroop Ghosh
2021 arXiv   pre-print
to address the above issues since they offer high density and consumes zero leakage power.  ...  This work identifies NVM vulnerabilities, attack vectors originating from device level all the way to circuits and systems considering both storage and compute applications.  ...  In [54] , a Differential Power Analysis (DPA) on STTRAM read/write operation and MRAM read operation are performed.  ... 
arXiv:2105.06401v1 fatcat:dwih3fdeuffpjduboiovfieyiu

2020 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 39

2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., +, TCAD Dec. 2020 5097-5110 Logic Locking With Provable Security Against Power Analysis Attacks.  ...  De, A., +, TCAD Dec. 2020 4453-4465 Logic Locking With Provable Security Against Power Analysis Attacks.  ...  ., +, TCAD Dec. 2020 4828-4841 High-Level Synthesis Design Space Exploration: Past, Present, and Future. Schafer, B.C., +, TCAD Oct. 2020  ... 
doi:10.1109/tcad.2021.3054536 fatcat:wsw3olpxzbeclenhex3f73qlw4

Hardware Functional Obfuscation With Ferroelectric Active Interconnects [article]

Tonggunag Yu, Yixin Xu, Shan Deng, Zijian Zhao, Nicolas Jao, You Sung Kim, Stefan Duenkel, Sven Beyer, Kai Ni, Sumitha George, Vijaykrishnan Narayanan
2021 arXiv   pre-print
Camouflaging gate techniques are typically used in hardware security to prevent reverse engineering.  ...  Our method utilizes only two FeFETs and an inverter to realize the masking function compared to recent reconfigurable logic gate implementations using several FeFETs and complex differential logic.  ...  structure for STT-MRAM 22 to realize a nonvolatile switch.  ... 
arXiv:2110.03855v1 fatcat:mropsrqnfzekhcfbc6qjacu4fm

2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26

2018 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
., see 2723-2736 , VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957  ...  Fan, X., +, Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell.  ...  Qi, X., +, TVLSI Nov. 2018 2494-2503 An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.  ... 
doi:10.1109/tvlsi.2019.2892312 fatcat:rxiz5duc6jhdzjo4ybcxdajtbq

Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities

Weiqiang Liu, Chongyan Gu, Maire O'Neill, Gang Qu, Paolo Montuschi, Fabrizio Lombardi
2020 Proceedings of the IEEE  
The principle is to save the most sensitive data in video applications in higher order 8T bit-cells while the lower order bits are stored in 6T bit-cells.  ...  [66] also proposed a voltage scalable architecture to save power dissipation by storing different "quality" data in various "quantity" of SRAM bit-cells.  ... 
doi:10.1109/jproc.2020.3030121 fatcat:vgxrxqkoibhgflrwq6rrfz7ofm

Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems

Priyadarshini Panda, Kaushik Roy
2020 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)  
He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design.  ...  I will also highlight some approaches towards cell-based assays to study drug effects and antibiotic resistance development.  ...  ) resilient to failures and malicious attacks.  ... 
doi:10.1109/vlsid49098.2020.00017 dblp:conf/vlsid/Panda020 fatcat:tvsoqomvynaxtkry62vhni4ura

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

2017 Electronics  
Electronics 2017, 6, 67 2 of 55 adopted to increase the effective number of bits for the SAR ADC.  ...  The uses of emerging technologies and lightweight encryption for correlation power analysis against side channel attack, silicon nanowire polymorphic gates, and all-spin logic devices for deception and  ...  Acknowledgments: The authors wish to thank Yu Bi for his early contribution on silicon nanowire camouflage, KATAN light-weight encryption and correlation power analysis.  ... 
doi:10.3390/electronics6030067 fatcat:ozssarlb2ng5pcdsupo2hljyna

2020-2021 Index IEEE Transactions on Computers Vol. 70

2021 IEEE transactions on computers  
Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name.  ...  Salami, B., +, TC Jan. 2021 72-82 Practical Resilience Analysis of GPGPU Applications in the Presence of Single-and Multi-Bit Faults.  ...  Kwon, T., +, TC Sept. 2021 1388-1400 Encryption Differential Fault Attack on Kreyvium & FLIP.  ... 
doi:10.1109/tc.2021.3134810 fatcat:p5otlsapynbwvjmqogj47kv5qa

2021 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 29

2021 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name.  ...  ., +, TVLSI Nov. 2021 1912-1921 Designing Efficient and High-Performance AI Accelerators With Custom-ized STT-MRAM.  ...  Hosseini, M., +, TVLSI Oct. 2021 1757-1770 Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM.  ... 
doi:10.1109/tvlsi.2021.3136367 fatcat:fwqswbyzejgfhgbzywrvsf2qgi

2018 Index IEEE Transactions on Computers Vol. 67

2019 IEEE transactions on computers  
., TC Sept. 2018 1259-1272 Analysis  ...  Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories.  ...  ., þ, TC Sept. 2018 1331-1340 Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories.  ... 
doi:10.1109/tc.2018.2882120 fatcat:j2j7yw42hnghjoik2ghvqab6ti
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