Filters








2,968 Hits in 3.0 sec

Secure Extension of FPGA General Purpose Processors for Symmetric Key Cryptography with Partial Reconfiguration Capabilities

Lubos Gaspar, Viktor Fischer, Lilian Bossuet, Robert Fouquet
2012 ACM Transactions on Reconfigurable Technology and Systems  
Secure extension of FPGA general purpose processors for symmetric key cryptography with partial reconfiguration capabilities. Abstract.  ...  We show that stringent separation of the cipher zone is helpful for partial reconfiguration of the security module, if the enciphering algorithm needs to be dynamically changed.  ...  Validation of the principle of security module partial reconfiguration in SRAM FPGAs The first solution from the previous section can be implemented in partially reconfigurable Xilinx FPGAs such as Virtex  ... 
doi:10.1145/2362374.2362380 fatcat:256kv3eq5bcefclicoeudjxcxy

In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs

Andreas Herkle, Holger Mandry, Joachim Becker, Maurits Ortmanns
2019 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)  
Therefore, this work presents an in-depth analysis of RO-PUFs on Xilinx Zynq-7000 FPGAs with a framework based on partial reconfiguration.  ...  Physical unclonable functions (PUFs) are excellent candidates to generate secret information on-chip without the need for secure storage.  ...  Partial Reconfiguration Framework Xilinx FPGAs support a partial reconfiguration flow, which enables dynamic reconfiguration of a dedicated area of the FPGA at runtime by loading a partial bitstream over  ... 
doi:10.1109/hst.2019.8740832 dblp:conf/host/HerkleMBO19 fatcat:5wvn66ifurgcjmgleiu33nqsxq

Secure Partial Reconfiguration of FPGAs

A.S. Zeineddini, K. Gaj
Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.  
In this paper, we investigate a method to perform a secure dynamic partial reconfiguration of SRAM FPGAs using embedded processor cores.  ...  Bitstream encryption and authentication are two most effective and practical solutions to improve the security of FPGAs.  ...  This method is capable of performing secure partial reconfiguration of the FPGA after the initial configuration.  ... 
doi:10.1109/fpt.2005.1568540 fatcat:piszg2jnufeonj5yljg4d2woni

A single-chip solution for the secure remote configuration of FPGAs using bitstream compression

Jo Vliegen, Nele Mentcns, Ingrid Verbauwhede
2013 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)  
In particular, bitstream compression in combination with partial reconfiguration is used to avoid the use of an external memory for the storage of the bitstream.  ...  This paper presents a system that allows the secure remote configuration of an FPGA, which is assumed to be the only device in the secure zone.  ...  Additionally, the communication of the FPGA updates is secured against various types of attacks. A. Partial reconfiguration Configuring an FPGA generally occurs in one iteration.  ... 
doi:10.1109/reconfig.2013.6732330 dblp:conf/reconfig/VliegenMV13 fatcat:z67vz4ajpjbs3lyinnikrqp5jq

Run-Time Re-configuration using FPGA for Bio-Medical Application

Mr. Ajinkya A. Bandegiri, Dr. Pradip C. Bhaskar
2018 International Journal of Trend in Scientific Research and Development  
In this research article, the runtime partial reconfiguration using VHDL coding in Xilinx tool has been performed.  ...  Partial Re-configuration can be used to maximize the resource utilization in FPGAs. The partial re configuration with FPGA can be used in Bio application at run-time.  ...  INTRODUCTION: The important feature of the FPGA is partial reconfiguration (PR), it is further sub divided in types: Dynamic partial reconfiguration (DPR) and Static Partial Reconfiguration.  ... 
doi:10.31142/ijtsrd10975 fatcat:56xs3gnejrdypcvo3viev3d3wq

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems [article]

Daniel Ziener
2018 arXiv   pre-print
In this treatise, my research on methods to improve efficiency, reliability, and security of reconfigurable hardware systems, i.e., FPGAs, through partial dynamic reconfiguration is outlined.  ...  The efficiency of reconfigurable systems can be improved by loading optimized data paths on-the-fly on an FPGA fabric.  ...  The research has been carried out in collaboration with several doctoral researchers, master and bachelor students from my research group Reconfigurable Computing. In  ... 
arXiv:1809.11156v1 fatcat:6ttulp2tancyvds7fk2coxoptq

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems

Chun-Hsian Huang, Pao-Ann Hsiung
2008 2008 13th Asia-Pacific Computer Systems Architecture Conference  
Hardware/software co-design Network security embedded system a b s t r a c t The dynamic partial reconfiguration technology of FPGA has made it possible to adapt system functionalities at run-time to changing  ...  As a solution, we proposed a novel UML-based hardware/software co-design platform (UCoP) targeting at dynamically partially reconfigurable network security systems (DPRNSS).  ...  Comparing conventional and dynamically partially reconfigurable network security systems We compare the conventional network security system with DPRNSS in terms of FPGA resource requirements and static  ... 
doi:10.1109/apcsac.2008.4625436 dblp:conf/aPcsac/HuangH08 fatcat:lyv6rkgzdfeafd2xqwzyeurmuq

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems

Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen
2010 Journal of systems architecture  
Hardware/software co-design Network security embedded system a b s t r a c t The dynamic partial reconfiguration technology of FPGA has made it possible to adapt system functionalities at run-time to changing  ...  As a solution, we proposed a novel UML-based hardware/software co-design platform (UCoP) targeting at dynamically partially reconfigurable network security systems (DPRNSS).  ...  Comparing conventional and dynamically partially reconfigurable network security systems We compare the conventional network security system with DPRNSS in terms of FPGA resource requirements and static  ... 
doi:10.1016/j.sysarc.2009.11.007 fatcat:tt26aeql5rd35epiko3b27arsy

Improving Correctness of Logic Circuit using Self-Healing Built-In Logic Test Module in FPGA using Dynamic Partial Reconfiguration

2019 International journal of recent technology and engineering  
Because of the reconfiguration nature of FPGAs, it become a good choice rather than ASIC on cloud.  ...  The security of hardware circuit which is transferred as bitstream to the FPGA board is of major concern for security critical applications.  ...  Module in FPGA using Dynamic Partial Reconfiguration Manjith B.C. algorithm.  ... 
doi:10.35940/ijrte.b2104.078219 fatcat:oflnngnomfdytevg2a65jbybta

Dynamically configurable security for SRAM FPGA bitstreams

Lilian Bossuet, Guy Gogniat, Wayne Burleson
2006 International Journal of Embedded Systems  
This proposition is distinct from other works because it uses the latest capabilities of SRAM FPGAs like partial dynamic reconfiguration and self-reconfiguration.  ...  This paper proposes a solution to improve the security of SRAM FPGAs through flexible bitstream encryption.  ...  Security configuration controller Our solution uses the partial configuration and the dynamic self-reconfiguration of the FPGA.  ... 
doi:10.1504/ijes.2006.010166 fatcat:s3xphvilkvbmhezlioklcxdlsa

Enhance Performance in Implementing the Security of Partially Reconfigurable Embedded Systems

Tran Thanh
2014 American Journal of Embedded Systems and Applications  
This paper presents a method to enhance safety and update speed of the partially reconfigurable embedded systems based on FPGA is updated remotely via the Internet or from external storage devices such  ...  System Security means protecting confidentiality and integrity of input or output data to as well as the safety of the system.  ...  The proposed model for DPR systems offers improved security and convenient reuse of external third-party IP cores.  ... 
doi:10.11648/j.ajesa.20140201.11 fatcat:ldz5kq7irjhdvlmch37e5b5hlq

Dynamic Partial Reconfiguration Implementation of AES Algorithm

Snehal Wankhade, Rashmi Mahajan
2014 International Journal of Computer Applications  
Hence to make it cost effective and to provide more secureness reconfigurable hardware such as FPGA is used with the concept of partial reconfiguration.  ...  This work reports Partial Reconfiguration (PR) by which selected areas of an FPGA can be reconfigured during runtime.  ...  Fig 1: AES Algorithm (Encryption) DYNAMIC PARTIAL RECONFIGURATION OF AES Dynamic partial reconfiguration is active partial reconfiguration, allows changing a part of the device while the rest of an FPGA  ... 
doi:10.5120/16986-7084 fatcat:ekaw3wn4wbfjfgtyjb5n6vwjtm

A system architecture for reconfigurable trusted platforms

Benjamin Glas, Alexander Klimm, Oliver Sander, Klaus Müller-Glaser, Jürgen Becker
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
This contribution discusses the feasibility of deploying ideas from trusted computing in the domain of reconfigurable hardware, esp. FPGAs, and possible benefits and drawbacks.  ...  For improving the security of embedded systems, trusted computing is a promising technology.  ...  It supports strong security requirements while maintaining the benefits of FPGA technology such as partial dynamic reconfiguration. This paper is structured as follows.  ... 
doi:10.1145/1403375.1403505 fatcat:py3dsnngbzdtvjc6eo77lh6aqu

IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs

Khoa Pham, Edson Horta, Dirk Koch, Anuj Vaishnav, Thomas Kuhn
2018 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)  
Systems designed by the proposed IPRDF are not only fully isolated but also support partial reconfiguration of insulated modules.  ...  This allows building secure and dependable systems that can use partial reconfiguration to mitigate from single-event upsets (SEUs) and that are more tolerant to aging and device imperfections.  ...  FPGA defects using partial reconfiguration.  ... 
doi:10.1109/mcsoc2018.2018.00018 dblp:conf/mcsoc/PhamHKVK18 fatcat:dlxpbrpxtnf3lpnq2cngboxccq

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

Maha Aboelmaged, Ali Shisha, Mohamed A. Abd El Ghany
2021 Electronics  
The system makes use of the ZedBoard's dynamic partial reconfiguration capability to shift between three distinct cipher algorithms: AEGIS, ASCON, and DEOXYS-II.  ...  The proposed design seeks to reduce the FPGA reconfiguration time by the application of LZ4 (Lempel-Ziv4) compression and decompression techniques on the ciphers' bitstream files.  ...  Dynamic Partial Reconfiguration DPR Definition Partial dynamic reconfiguration is a feature available in FPGAs that enables the changing of the design implemented on the FPGA during its runtime [17]  ... 
doi:10.3390/electronics10161989 fatcat:j3f7karmmzhrhcaopc5vglgdfe
« Previous Showing results 1 — 15 out of 2,968 results