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Integrated Timing Analysis of Application and Operating Systems Code

Lee Kee Chong, Clement Ballabriga, Van-Thuan Pham, Sudipta Chattopadhyay, Abhik Roychoudhury
2013 2013 IEEE 34th Real-Time Systems Symposium  
In this work, we present a framework for RTOS aware WCET analysis -where the timing effects of system calls and interrupts can be accounted for.  ...  We show the use of our analysis to compute the worst-case response time for a real-life robot controller software which runs several tasks such as balancing and/or navigation on top of a real-time operating  ...  The delay caused by these additional cache misses is known as cache related preemption delay (CRPD).  ... 
doi:10.1109/rtss.2013.21 dblp:conf/rtss/ChongBPCR13 fatcat:2vbnbr7utfeg5eqzhv6okycyyq

Worst-Case Energy-Consumption Analysis by Microarchitecture-Aware Timing Analysis for Device-Driven Cyber-Physical Systems

Phillip Raffeck, Christian Eichler, Peter Wägemann, Wolfgang Schröder-Preikschat, Michael Wagner
2019 Worst-Case Execution Time Analysis  
However, as we demonstrate in this paper, existing approaches from microarchitecture-aware timing analysis (i.e., considering cache and pipeline effects) are beneficial for determining WCEC bounds: We  ...  extended our framework on whole-system analysis with microarchitecture-aware timing modeling to precisely account for the execution time that devices are kept (in)active.  ...  of caches, and especially cache-related preemption delays in the fixed-priority scheduling scheme.  ... 
doi:10.4230/oasics.wcet.2019.4 dblp:conf/wcet/RaffeckEWS19 fatcat:vnk7phhis5dx7nmh36wqhkeufa

Response-time analysis for fixed-priority systems with a write-back cache

Robert I. Davis, Sebastian Altmeyer, Jan Reineke
2018 Real-time systems  
-Finally, while data-cache analysis is not the main focus of the paper, we review related work in this area in the Appendix.  ...  This paper introduces analyses of write-back caches integrated into response-time analysis for fixed-priority preemptive and non-preemptive scheduling.  ...  Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution  ... 
doi:10.1007/s11241-018-9305-z fatcat:7jp6mshpove7ti2yjyayqrahqu

A Survey on Static Cache Analysis for Real-Time Systems

Mingsong Lv, Nan Guan, Jan Reineke, Reinhard Wilhelm, Wang Yi
2015 Leibniz Transactions on Embedded Systems  
Then, the discussion is extended to cache analysis in complex execution environment, followed by a survey of existing tools based on static techniques for cache analysis.  ...  We first present the challenges and static analysis techniques for independent programs with respect to different cache features.  ...  The extra delay due to cache reloading is commonly referred to as the Cache-Related Preemption Delay (CRPD).  ... 
doi:10.4230/lites-v003-i001-a005 dblp:journals/lites/LvGRW016 fatcat:ax5h3hurpbekjo52thkaduwtki

Message from the Workshop Chair

2005 2005 International Conference on Cyberworlds (CW'05)  
The aim of the workshop is to provide a forum for discussing current trends and issues related to the timing analysis of Real-Time Systems with special emphasis on bridging the gap between industry and  ...  related to object oriented programming models. ¡ On low-level analysis techniques the focus is on modelling timing behaviour of processor features such as cache effects, branch prediction and speculative  ...  Acknowledgements Many members of the compiler design group at the University of the Saarland, especially the members of the USES (University of the Saarland Embedded Systems) group, deserve acknowledgement  ... 
doi:10.1109/cw.2005.66 dblp:conf/cw/XX05a fatcat:ubjg3eboa5cojl5mrrgucd42ae

Optimal Selection of Preemption Points to Minimize Preemption Overhead

Marko Bertogna, Orges Xhani, Mauro Marinoni, Francesco Esposito, Giorgio Buttazzo
2011 2011 23rd Euromicro Conference on Real-Time Systems  
These values are significantly influenced by the preemption overhead, which mainly includes the cache related delays and the context switch times introduced by each preemption.  ...  In a previous work, we presented a method for the optimal selection of preemption points under the restrictive assumption of a fixed preemption cost, identical for each preemption point.  ...  Then, a preemption point is placed in each interval, at the location having the smallest number of useful cache blocks, i.e., cached data that will be accessed again.  ... 
doi:10.1109/ecrts.2011.28 dblp:conf/ecrts/BertognaXMEB11 fatcat:b3aeaf7otzh7pkcy4fgg242tr4

Overhead-Aware Schedulability Evaluation of Semi-Partitioned Real-Time Schedulers

Pedro Souto, Paulo Baltarejo Sousa, Robert I. Davis, Konstantinos Bletsas, Eduardo Tovar
2015 2015 IEEE 21st International Conference on Embedded and Real-Time Computing Systems and Applications  
In this paper, we provide an overhead-aware schedulability analysis based on demand bound functions for two hard real-time semi-partitioned scheduling algorithms, EDF-WM and C=D.  ...  The analysis is used to guide the respective off-line task assignment and splitting procedures.  ...  The cache line evictions caused by task preemption or migration may cause significant overheads referred to as cache related preemption delays (CRPD) or cache related preemption and migration delays (CPMD  ... 
doi:10.1109/rtcsa.2015.13 dblp:conf/rtcsa/SoutoSDBT15 fatcat:a746s5swjbbe5nfx2roohvk4ue

Improved cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems

Sebastian Altmeyer, Robert I. Davis, Claire Maiza
2012 Real-time systems  
In such systems, cache related pre-emption delays can be a significant proportion of task execution times.  ...  set size, reuse, and block reload times.  ...  We also like to thank Alan Burns, Jack Whitham and the anonymous reviewers for their comments on an earlier draft of this paper.  ... 
doi:10.1007/s11241-012-9152-2 fatcat:t6k3okbv2fhlbkocvzm62ho5nq

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

Giovani Gracioli, Ahmed Alhammad, Renato Mancuso, Antônio Augusto Fröhlich, Rodolfo Pellizzoni
2015 ACM Computing Surveys  
Multicore processors are being extensively used by real-time systems, mainly because of their demand for increased computing power.  ...  One of the main factors for unpredictability in a multicore processor is the cache memory hierarchy.  ...  Then, this information is used to lock cache lines.  ... 
doi:10.1145/2830555 fatcat:nckhashqprghfnbcaqqu7vk5vi

Towards Predictable Real-Time Performance on Multi-Core Platforms [article]

Hyoseung Kim
2016 arXiv   pre-print
such as caches, memory buses, and I/O devices.  ...  Specifically, we tackle the issues of cache and memory contention, locking and synchronization, interrupt handling, and access control for computational accelerators such as GPGPUs, all of which are crucial  ...  preemption delay due to τ h . τ l also has one cache warm-up delay and one cache-related preemption delay.  ... 
arXiv:1607.08578v1 fatcat:2ndmimzpxbehzlntoppabtusbq

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

Claire Maiza, Hamza Rihani, Juan M. Rivas, Joël Goossens, Sebastian Altmeyer, Robert I. Davis
2019 ACM Computing Surveys  
A detailed review is provided covering four main categories: full integration, temporal isolation, integrating interference efects into schedulability analysis, and mapping and allocation.  ...  The survey highlights the key issues involved in providing guarantees of timing correctness for multi-core systems.  ...  research on analysis of NoCs.  ... 
doi:10.1145/3323212 fatcat:mn6xmduiyjfgzhemn5s2lmfgje

Arbitration-Induced Preemption Delays

Farouk Hebbache, Florian Brandner, Mathieu Jan, Laurent Pautet, Michael Wagner
2019 Euromicro Conference on Real-Time Systems  
These blocking delays may induce significant jitter and consequently increase the tasks' response times. This work explores means to manage and, finally, bound these blocking delays.  ...  The interactions among concurrent tasks pose a challenge in the design of real-time multi-core systems, where blocking delays that tasks may experience while accessing shared memory have to be taken into  ...  Phases without main memory activity may only access data stored in a scratchpad. Preemption-related delays due to memory accesses thus cannot appear.  ... 
doi:10.4230/lipics.ecrts.2019.19 dblp:conf/ecrts/HebbacheBJP19 fatcat:2p2zxzx6crb2fhmzxu2lzaf5nm

Düppel

Yinqian Zhang, Michael K. Reiter
2013 Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security - CCS '13  
Düppel includes defenses for timeshared caches such as per-core L1 and L2 caches.  ...  This paper presents the design, implementation and evaluation of a system called Düppel that enables a tenant virtual machine to defend itself from cache-based side-channel attacks in public clouds.  ...  Weidong Cui and the anonymous reviewers for suggestions that led to improvements to this paper.  ... 
doi:10.1145/2508859.2516741 dblp:conf/ccs/ZhangR13 fatcat:axty5jofjncqdljxz6cxgasa6m

Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds

Timon Kelter, Heiko Falk, Peter Marwedel, Sudipta Chattopadhyay, Abhik Roychoudhury
2011 2011 23rd Euromicro Conference on Real-Time Systems  
We implemented a prototype tool which uses the new analysis and tested it on a set of realworld benchmarks.  ...  In the domain of real-time systems, the analysis of the timing behavior of programs is crucial for guaranteeing the schedulability and thus the safeness of a system.  ...  With this notion of basic blocks and the results from the other microarchitectural analyses which yield WCET values for the blocks without bus accesses, we can formulate the offset analysis as a data flow  ... 
doi:10.1109/ecrts.2011.9 dblp:conf/ecrts/KelterFMCR11 fatcat:lxkfioq4vzh5tgdff4dgrd7iq4

Dynamic Cache Switching in Reconfigurable Embedded Systems

John Shield, Peter Sutton, Philip Machanick
2007 2007 International Conference on Field Programmable Logic and Applications  
Block Size  ...  The idea of changing cache attributes to suit an application has been explored for single programs.  ...  Some related work in the area of task switching looks into cache-related preemptive delay [4] [5] [6] .  ... 
doi:10.1109/fpl.2007.4380634 dblp:conf/fpl/ShieldSM07 fatcat:gw5w72oxbzcqtfpjmkeuluqgp4
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