Filters








59,591 Hits in 4.0 sec

Evolutionary Algorithm for Solving Multi-Mode Resource Constrained Project Scheduling Problems through Deterministic Mode Selection

Shivam Agarwal, Tushar Bhat
2013 International Journal of Computer Applications  
General Terms Project scheduling, evolutionary algorithm, deterministic mode selection.  ...  This work describes a novel approach towards solving Multimode Resource Constrained Project Scheduling (MRCPS) Problems and an algorithm developed to implement this approach.  ...  This shows that with optimum mode selection, the probability of obtaining optimum schedule through stochastic selection becomes very high. ii) Implementation of Optimisation and Refinement phases separately  ... 
doi:10.5120/13582-1316 fatcat:4pcda7nh3vbk5fe6tgbmh2ksse

SimLack: Simulation-based Optimization and Scheduling of Generic Powder Coating Lines

Lukas Hollenstein, Adrian Lötscher, Fabian Luccarini
2019 SNE Simulation Notes Europe  
through simulation-based optimization.  ...  We discuss how these two aspects of the system render it an important innovation for the painting line industry and show first results from the scheduling system.  ...  This work is supported by the Commission for Technology and Innovation (CTI) of the Swiss Confederation through grant number 17655.1 PFEN-ES.  ... 
doi:10.11128/sne.29.tn.10483 fatcat:h2trxk734vfjdfk4t6l7h46ndm

A design-based model for the reduction of software cycle time

K.W. Collier, J.S. Collofello
1996 Proceedings of HICSS-29: 29th Hawaii International Conference on System Sciences  
This model aims to shorten cycle time by shortening the implementation phase through design and schedule refinement.  ...  Through a schedule analysis, the model guides the designer to focus refinement efforts on the most beneficial system components.  ... 
doi:10.1109/hicss.1996.495527 dblp:conf/hicss/CollierC96 fatcat:34xnh4g5uvgybimj5ek5njg23y

Schedule Integration Framework for Time-Triggered Automotive Architectures

Florian Sagstetter, Sidharta Andalam, Peter Waszecki, Martin Lukasiewycz, Hauke Stähle, Samarjit Chakraborty, Alois Knoll
2014 Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14  
This modular design approach is enabled by a novel methodology for schedule integration where local schedules are defined independently for subsystems before being integrated into a global schedule.  ...  As a remedy, we propose a framework for modular architectures based on a data-centric description and a fully time-triggered scheduling.  ...  The focus of this paper is not to obtain a globally optimal schedule, but rather to integrate locally optimized application configurations according to their specific requirements.  ... 
doi:10.1145/2593069.2593211 dblp:conf/dac/SagstetterAWLSCK14 fatcat:7pwrigrawvgm5goz7jozlsbn4a

Early evaluation techniques for low power binding

E. Kursun, A. Srivastava, S.G. Memik, M. Sarrafzadeh
2002 Proceedings of the International Symposium on Low Power Electronics and Design  
An experimental flow that integrates path-based scheduling, power optimal binding and power driven iterative rescheduling stages is constructed.  ...  Experimental results on DFGs from MediaBench suit also demonstrate the fact that metric evaluation is on average 42.6 times faster than performing optimal binding and iterative power improvement.  ...  Rescheduling for Low Power Most synthesis methodologies utilize iterative refinement to improve the final design.  ... 
doi:10.1109/lpe.2002.146730 fatcat:pcfgyrprubh53cmyg4l2uardrm

Early evaluation techniques for low power binding

Eren Kursun, Ankur Srivastava, Seda Ogrenci Memik, Majid Sarrafzadeh
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
An experimental flow that integrates path-based scheduling, power optimal binding and power driven iterative rescheduling stages is constructed.  ...  Experimental results on DFGs from MediaBench suit also demonstrate the fact that metric evaluation is on average 42.6 times faster than performing optimal binding and iterative power improvement.  ...  Rescheduling for Low Power Most synthesis methodologies utilize iterative refinement to improve the final design.  ... 
doi:10.1145/566408.566450 dblp:conf/islped/KursunSMS02 fatcat:isixxlwcifagnkqxs3ei23stlm

Early evaluation techniques for low power binding

Eren Kursun, Ankur Srivastava, Seda Ogrenci Memik, Majid Sarrafzadeh
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
An experimental flow that integrates path-based scheduling, power optimal binding and power driven iterative rescheduling stages is constructed.  ...  Experimental results on DFGs from MediaBench suit also demonstrate the fact that metric evaluation is on average 42.6 times faster than performing optimal binding and iterative power improvement.  ...  Rescheduling for Low Power Most synthesis methodologies utilize iterative refinement to improve the final design.  ... 
doi:10.1145/566448.566450 fatcat:tabumaf7wffcllhybnbfimv77m

Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture

Juinn-Dar HUANG, Chia-I CHEN, Yen-Ting LIN, Wan-Ling HSU
2011 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
In this article, we propose a new resourceconstrained communication synthesis algorithm for optimizing both interisland connections (IICs) and latency targeting on distributed registerfile microarchitecture  ...  and latency can be achieved respectively as compared to the previous work. key words: communication synthesis, distributed register-file microarchitecture, interconnect minimization, resource binding, scheduling  ...  In each iteration, two operations, island assignment (binding) and IIC refinement (rescheduling and rebinding), are applied consecutively.  ... 
doi:10.1587/transfun.e94.a.1151 fatcat:2wem74t6fnecdeiz4bpiiylkry

Scheduling for functional pipelining and loop winding

Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
1991 Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91  
We optimize both the initiationinterval and the turnaroundtime of a schedule.  ...  The novel feature which differs our approach from others is that the scheduled operations are iteratively moved up and down to accommodate the ready yet unscheduled operations.  ...  We solve it by performing a pipeline-schedule iteration which consists of (a) assigning new operations to the current block. @) preassigning operations to the future blocks and (c) iteratively refining  ... 
doi:10.1145/127601.127766 dblp:conf/dac/HwangHL91 fatcat:4533dnygk5eqrdzjugrwm4346i

Joint Algorithm Developing and System-Level Design: Case Study on Video Encoding [chapter]

Jiaxing Zhang, Gunar Schirner
2013 IFIP Advances in Information and Communication Technology  
It empowers the designer to combine analysis results across environments, apply cross layer optimizations, which will yield an overall optimized design through rapid design iterations.  ...  Through applying our unified design flow, an improved HW/SW is found yielding 50% performance gain compared to a pure software solution.  ...  Through its simulation analysis, the designer improves the algorithm for optimizing functional performance.  ... 
doi:10.1007/978-3-642-38853-8_3 fatcat:uxpqb5jflrhe3befld6k4r3t3e

Optimum and heuristic synthesis of multiple word-length architectures

G.A. Constantinides, P.Y.K. Cheung, W. Luk
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Techniques are introduced to perform scheduling with incomplete word-length information, to combine binding and word-length selection, and to refine word-length information based on critical path analysis  ...  This paper explores the problem of architectural synthesis (scheduling, allocation, and binding) for multiple word-length systems.  ...  The algorithm arrives at a solution through an iterative refinement of word-length information in order to reach the user-specified latency target .  ... 
doi:10.1109/tvlsi.2004.840398 fatcat:sgg7nbp5hjdevi22wzj2cyr4bm

Multilevel Initialization for Layer-Parallel Deep Neural Network Training [article]

Eric C. Cyr and Stefanie Günther and Jacob B. Schroder
2019 arXiv   pre-print
To do this, we apply a refinement strategy across the time domain, that is equivalent to refining in the layer dimension.  ...  We investigate the effectiveness of such multilevel "nested iteration" strategies for network training, showing supporting numerical evidence of reduced run time for equivalent accuracy.  ...  In the top image a schedule with 200, 100, and 50 optimization iterations on the coarse to the fine level is used by nested iteration.  ... 
arXiv:1912.08974v1 fatcat:j3wxoyu375hmtmdba2gkntgqoa

Scheduling Issues in Optimistic Parallelization

Milind Kulkarni, Keshav Pingali
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
We demonstrate this through the motivating example of Delaunay mesh refinement, an irregular algorithm, which we have parallelized optimistically using the Galois system.  ...  We apply several scheduling policies to this algorithm and investigate their performance, showing that careful consideration of scheduling is necessary to maximize parallel performance.  ...  Scheduling Optimistic parallelism is a viable approach to concurrent execution as long as the optimism is warranted.  ... 
doi:10.1109/ipdps.2007.370491 dblp:conf/ipps/KulkarniP07 fatcat:dzfvmjrtajddrhogfgb3qwqiby

Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture

Ya-Shih HUANG, Yu-Ju HONG, Juinn-Dar HUANG
2009 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global  ...  It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal  ...  Iteration Refinement Phase The Iterative refinement process iteratively invokes CPR and CTS to reroute and reschedule the data transfers.  ... 
doi:10.1587/transfun.e92.a.3143 fatcat:auox3ejjb5f25eblruugro25vy

An efficient algorithm for multi-domain clock skew scheduling

Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng
2011 2011 Design, Automation & Test in Europe  
Even though this problem can be formulated as a mixed integer linear programming (MILP), it is expensive to solve optimally in general.  ...  Multi-domain clock skew scheduling was proposed to tackle this impracticality by constraining the total number of clock delays.  ...  Columns "#Vertices" and "#Edges" show the number of vertices and edges in the timing constraint graph respectively, while Column "T ∞ cycle " reports the optimal cycle period achievable through unconstrained  ... 
doi:10.1109/date.2011.5763220 dblp:conf/date/ZhiLZYZZ11 fatcat:djilaxkcpjaihknpikby7h3hee
« Previous Showing results 1 — 15 out of 59,591 results