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Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narvaez, Joel Emer
2012 SIGARCH Computer Architecture News  
This paper proposes Performance Impact Estimation (PIE) as a mechanism to select the appropriate workloadto-core mapping in a heterogeneous multi-core processor.  ...  This paper proposes Performance Impact Estimation (PIE) as a mechanism to predict which workload-to-core mapping is likely to provide the best performance.  ...  Kenzo Van Craeynest is supported through a doctoral fellowship by the Agency for Innovation by Science and Technology (IWT).  ... 
doi:10.1145/2366231.2337184 fatcat:qp3ieadxevea5bwvgnetdl3uiq

Scheduling heterogeneous multi-cores through performance impact estimation (PIE)

Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narvaez, Joel Emer
2012 2012 39th Annual International Symposium on Computer Architecture (ISCA)  
This paper proposes Performance Impact Estimation (PIE) as a mechanism to select the appropriate workloadto-core mapping in a heterogeneous multi-core processor.  ...  This paper proposes Performance Impact Estimation (PIE) as a mechanism to predict which workload-to-core mapping is likely to provide the best performance.  ...  Kenzo Van Craeynest is supported through a doctoral fellowship by the Agency for Innovation by Science and Technology (IWT).  ... 
doi:10.1109/isca.2012.6237019 dblp:conf/isca/CraeynestJENE12 fatcat:bae7ytbzfresln55icmqkvyxeq

Starchart: hardware and software optimization using recursive partitioning regression trees

Kenzo Van Craeynest, Shoaib Akram, Wim Heirman, Aamer Jaleel, Lieven Eeckhout
2013 Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques  
scheduling improves performance by 32% on average for heterogeneous multi-threaded workloads.  ...  Yet, guaranteeing that all threads make equal progress on heterogeneous multi-cores is of utmost importance for both multi-threaded and multi-program workloads to improve performance and quality-of-service  ...  Kenzo Van Craeynest was supported through a doctoral fellowship by the Agency for Innovation by Science and Technology (IWT). Additional support is provided by the FWO project G.0179. 10  ... 
doi:10.1109/pact.2013.6618815 dblp:conf/IEEEpact/CraeynestAHJE13 fatcat:p6ixpmsr4rdxph7uajkdm6iori

Mage: Online Interference-Aware Scheduling in Multi-Scale Heterogeneous Systems [article]

Francisco Romero, Christina Delimitrou
2018 arXiv   pre-print
Heterogeneity has grown in popularity both at the core and server level as a way to improve both performance and energy efficiency.  ...  Across 350 application mixes on a heterogeneous CMP, Mage improves performance by 38% and up to 2x compared to a greedy scheduler.  ...  accounts for resource contention, while PIE only focuses on the impact of core heterogeneity on performance.  ... 
arXiv:1804.06462v1 fatcat:zddhenvoevar7hyvcr6nbv5pua

Apportioning slices of a growing pie $b : Examining the influence of Top Management Team (TMT) credentials on firm value creation and its distribution between the firm's shareholders and it's TMT / $c Timothy Lewis Cecil

Carl Joachim Kock
2021 Zenodo  
Although management literature today presents an abundant amount of research on value creation (Datta and Iskandar-Datta, 2014, Boyd, Bergh and Ketchen, 2010) executive compensation and firm performance  ...  The second step entails estimating the impact of team wins on the team's total revenue.  ...  impact both performance and compensation I will now analyze the impact.  ... 
doi:10.5281/zenodo.5545805 fatcat:ojm3fnmie5djjm77uo3uqpovoe

Power-performance modeling on asymmetric multi-cores

Mihai Pricopi, Thannirmalai Somu Muthukaruppan, Vanchinathan Venkataramani, Tulika Mitra, Sanjay Vishin
2013 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)  
Limited number of performance counters and heterogeneous memory hierarchy increase the difficulty in predicting the performance and power consumption across cores in commercial asymmetric multi-core architectures  ...  In this work, we propose a software-based modeling technique that can estimate performance and power consumption of workloads for different core types.  ...  The online scheduling in heterogeneous multi-cores can be improved significantly by estimating performance across all the core types [22] . Craeynest et al.  ... 
doi:10.1109/cases.2013.6662519 dblp:conf/cases/PricopiMVMV13 fatcat:cupbu6cgcbc5xau4blnwmjnkce

Understanding fundamental design choices in single-ISA heterogeneous multicore architectures

Kenzo Van Craeynest, Lieven Eeckhout
2013 ACM Transactions on Architecture and Code Optimization (TACO)  
Two core types provide most of the benefits from heterogeneity and a larger number of core types does not contribute much; job-to-core mapping is both important and challenging for heterogeneous multicore  ...  metrics; and how fundamental design choices, such as core type, cache size, and off-chip bandwidth, affect performance.  ...  on the impact of core types initially and study the fundamental impact of core types on heterogeneous multicore performance.)  ... 
doi:10.1145/2400682.2400691 fatcat:5qkv7eaaljhsxp4lvsovf6liia

Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors

Ying Zhang, Lide Duan, Bin Li, Lu Peng, Srinivasan Sadagopan
2015 Microprocessors and microsystems  
In recent years, single-ISA heterogeneous chip multiprocessors (CMP) consisting of big high-performance cores and small power-saving cores on the same die have been proposed for the exploration of high  ...  Our strategy is capable of significantly reducing the energy consumption while delivering comparable performance to a recently proposed heterogeneous scheduler (MLP-ratio), thus improving the energy-efficiency  ...  More recently, Craeynest et al. present a heterogeneous scheduler via performance impact estimation (PIE) [8] .  ... 
doi:10.1016/j.micpro.2015.04.008 fatcat:2prvl73am5ezdpphe6g7phrnna

Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies

Po-An Tsai, Changping Chen, Daniel Sanchez
2018 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)  
AMS monitors threads, accurately models their performance under different hierarchies and core types, and adapts algorithms first proposed for cache partitioning to produce high-quality schedules.  ...  AMS is cheap enough to use online, so it adapts to program phases, and performs within 1% of an exhaustive-search scheduler.  ...  To map threads across heterogeneous cores, PIE estimates each thread's CPI on different core types.  ... 
doi:10.1109/micro.2018.00058 dblp:conf/micro/TsaiCS18 fatcat:cnbwt3d23rdk7jxzf64mnzduum

Compiler Enhanced Scheduling for OpenMP for Heterogeneous Multiprocessors [article]

Jyothi Krishna V S, Shankar Balachandran
2018 arXiv   pre-print
Scheduling in Asymmetric Multicore Processors (AMP), a special case of Heterogeneous Multiprocessors, is a widely studied topic.  ...  On an average, we see 18% reduction in runtime and 14% reduction in energy consumption in standard NPB and FSU benchmarks with CES across multiple frequencies and core configurations in big.LITTLE.  ...  In PIE (Performance Impact Estimation) [20] , hardware counters for CPI, ILP and MLP are used to estimate the performance that can be achieved, if the thread was to run in other type of core at run-time  ... 
arXiv:1808.06074v1 fatcat:u3saoouzjveynmvrwn2ora7r64

CuttleSys: Data-Driven Resource Management forInteractive Applications on Reconfigurable Multicores [article]

Neeraj Kulkarni, Gonzalo Gonzalez-Pumariega, Amulya Khurana, Christine Shoemaker, Christina Delimitrou, David Albonesi
2020 arXiv   pre-print
We present CuttleSys, a runtime for reconfigurable multi-cores that leverages scalable and lightweight data mining to quickly identify suitable core and cache configurations for a set of co-scheduled applications  ...  Multi-tenancy for latency-critical applications leads to re-source interference and unpredictable performance.  ...  Ghose, “Flexcore: A reconfigurable processor “Scheduling heterogeneous multi-cores through performance impact supporting flexible, dynamic morphing,” in 2015 IEEE 22nd  ... 
arXiv:2008.00329v1 fatcat:ixlacql2srfsldcosl6wpbldua

A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors

Sparsh Mittal
2016 ACM Computing Surveys  
To meet the needs of diverse range of workloads, asymmetric multicore processors (AMPs) have been proposed, which feature cores of different microarchitecture or ISAs.  ...  We hope that more than just synthesizing the existing work on AMPs, the contribution of this survey will be to spark novel ideas for architecting future AMPs that can make a definite impact on the landscape  ...  Use of CPI stack Van Craeynest et al. [2012] present a model, named performance impact estimation (PIE) to predict the best application-to-core mapping.  ... 
doi:10.1145/2856125 fatcat:3hda47vtl5fznfvbskwcm2cbo4

LPM: Concurrency-Driven Layered Performance Matching

Yu-Hang Liu, Xian-He Sun
2015 2015 44th International Conference on Parallel Processing  
We also have achieved noticeable performance improvement by simply adopting smart LPM scheduling without changing the underlying hardware configurations.  ...  It reveals the fact that increasing the effective overlapping between hits and misses of the higher layer will alleviate the performance impact of the lower layer.  ...  Scheduling heterogeneous multi-cores through performance impact estimation (PIE) [23] requires a data stall time formula. However, the PIE uses an approximate formula that is inaccurate.  ... 
doi:10.1109/icpp.2015.97 dblp:conf/icpp/LiuS15 fatcat:l2pctolh6rclhin5hktnql6ile

Exploring Fine-Grained Heterogeneity with Composite Cores

Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott Mahlke
2016 IEEE transactions on computers  
Heterogeneous multicore systems-comprising multiple cores with varying performance and energy characteristics-have emerged as a promising approach to increasing energy efficiency.  ...  We propose Composite Cores, an architecture that reduces migration overheads by bringing heterogeneity into a core.  ...  [2] show the performance benefits of heterogeneous multi-cores for multithreaded applications on a prototype with different frequency settings per core. Kwon et al.  ... 
doi:10.1109/tc.2015.2419669 fatcat:3a2efbi7grg7fli3wsi4kakttm

Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors

Ying Zhang, Lide Duan, Bin Li, Lu Peng, Srinivasan Sadagopan
2014 Fifteenth International Symposium on Quality Electronic Design  
In recent years, single-ISA heterogeneous chip multiprocessors (CMP) consisting of big high-performance cores and small power-saving cores on the same die have been proposed for the exploration of high  ...  Our strategy is capable of significantly reducing the energy consumption while delivering comparable performance to a recently proposed heterogeneous scheduler (MLP-ratio), thus improving the energyefficiency  ...  More recently, Craeynest et al. present a heterogeneous scheduler via performance impact estimation (PIE) [5] . There are few studies addressing energy minimization on heterogeneous platforms.  ... 
doi:10.1109/isqed.2014.6783390 dblp:conf/isqed/ZhangDLPS14 fatcat:dvqmwnjbmjajhjala7xwruk3v4
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