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Scheduling System Verification [chapter]

Pao-Ann Hsiung, Farn Wang, Yue-Sun Kuo
1999 Lecture Notes in Computer Science  
A formal framework is proposed for the verification of complex realtime systems, modeled as client-server scheduling systems, using the popular model-checking approach.  ...  Model-checking is often restricted by the large statespace of complex real-time systems. The scheduling of tasks in such systems can be taken advantage of for model-checking.  ...  scheduling system, our target system of verification consists of a constant number m of servers that perform scheduling and a constant number n of clients that issue scheduling requests.  ... 
doi:10.1007/3-540-49059-0_2 fatcat:myqfwujgpnde7bzzmblyfmnhae

Formal verification of real-time systems with preemptive scheduling

Didier Lime, Olivier (H. ) Roux
2008 Real-time systems  
In this paper, we propose a method for the verification of timed properties for real-time systems featuring a preemptive scheduling policy: the system, modeled as a scheduling time Petri net, is first  ...  The proposed modeling and verification method are generic enough to account for many scheduling policies.  ...  Issues of formal verification of real-time systems State-space computation.  ... 
doi:10.1007/s11241-008-9059-0 fatcat:rtb3mb3ogfc3bdz553qvhhfvai

Schedule Verification and Synthesis for Embedded Real-Time Components [chapter]

Purandar Bhaduri
2007 Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems  
In this paper we address the problems of schedule synthesis and timing verification for component based architectures in embedded systems.  ...  We solve the associated synthesis and verification problems using the framework of timed interface automata and timed games.  ...  Timing Verification and Schedule Synthesis In this section, we explain how the timing verification and schedule synthesis problems can be viewed as an instance of a timed game (see [Maler et al., 1995  ... 
doi:10.1007/978-1-4020-6254-4_11 fatcat:oey4csowijclda53sn5g4it2hi

Compositional Verification for Hierarchical Scheduling of Real-Time Systems

Laura Carnevali, Alessandro Pinzuti, Enrico Vicario
2013 IEEE Transactions on Software Engineering  
system applications.  ...  This enables exact verification of intra-application constraints and approximate but safe verification of interapplication constraints.  ...  Also note that integration of the state-spaces of individual applications would open the way to compositional verification of non-HS systems running under FP preemptive scheduling.  ... 
doi:10.1109/tse.2012.54 fatcat:bn4bzl72hngtpgbhidfgqa2pkq

Scheduling Design and Verification for Open Soft Real-Time Systems

Robert Glaubius, Terry Tidwell, William D. Smart, Christopher Gill
2008 2008 Real-Time Systems Symposium  
In previous work we established foundations for a scheduling policy design and verification approach for open soft real-time systems, that can use different decision models, e.g., a Markov Decision Process  ...  of a wider range of scheduling policies for open soft real-time systems  ...  This paper presents several novel advances in the design and verification of scheduling policies for open soft realtime systems.  ... 
doi:10.1109/rtss.2008.48 dblp:conf/rtss/GlaubiusTSG08 fatcat:ep7rd3ptmzfhtbg7vlzo3bvfuq

Schedulability Analysis and Symbolic Verification Method for Heterogeneous Multicore Real-Time Systems

Wei Wang
2017 International Journal of Performability Engineering  
the schedulability of selected systems.  ...  One key attribute of real-time systems is the schedulability that guarantees to satisfy the timing requirements.  ...  UPPAAL-based CPU-GPU Heterogeneous System Schedulability Verification In this section, we utilized UPPAAL [5] as the verification tool, to verify the schedulability of CPU-GPU heterogeneous systems.  ... 
doi:10.23940/ijpe.17.06.p1.785795 fatcat:n4jxc64ufna7lojwm4cd7hn4cm

Formal verification of concurrent scheduling strategies using TLA

Gudmund Grov, Greg Michaelson, Andrew Ireland
2007 2007 International Conference on Parallel and Distributed Systems  
There is a high demand for correctness for safety critical systems, often requiring the use of formal verification.  ...  Simple, well-understood scheduling strategies ease verification but are often very inefficient. In contrast, efficient concurrent schedulers are often complex and hard to reason about.  ...  Due to the concurrent, rather than sequential, nature of distributed systems, composition of prepost conditions of components, as found in e.g. Hoare logic [10] , is not valid for such verification.  ... 
doi:10.1109/icpads.2007.4447839 dblp:conf/icpads/GrovMI07 fatcat:p5zggcqt7fcgfppluchz7wer5e

A Formal Approach to Design and Verification of Two-Level Hierarchical Scheduling Systems [chapter]

Laura Carnevali, Giuseppe Lipari, Alessandro Pinzuti, Enrico Vicario
2011 Lecture Notes in Computer Science  
Hierarchical scheduling (HS) systems manage a set of realtime applications through a scheduling hierarchy, enabling partitioning and reduction of complexity, confinement of failure modes, and temporal  ...  isolation among system applications.  ...  We extend here the approach of [8] to enable design and verification of HS systems managed by a TDM global scheduler and FP local schedulers.  ... 
doi:10.1007/978-3-642-21338-0_9 fatcat:k42vc52pabbe7fb6sax55slucy

Clock schedule verification with crosstalk

Hai Zhou
2002 Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02  
In sequential circuits with transparent latches, crosstalk makes the clock schedule verification even harder.  ...  A novel algorithm is given for clock schedule verification in the presence of crosstalk and primary experiments show promising results.  ...  CLOCK SCHEDULE VERIFICATION WITH CROSSTALK Our approach to clock schedule verification in the presence of crosstalk is based on the new timing window based formulation presented in Section 4.  ... 
doi:10.1145/589411.589428 dblp:conf/tau/Zhou02 fatcat:fqepx3dzyzep3ajknvc7lxyiym

Verification of Optimized Energy-Saving Train Scheduling Utilizing Automatic Train Operation System

Shoichiro Watanabe, Yasuhiro Sato, Takafumi Koseki, Takeshi Mizuma, Ryuji Tanaka, Yoshihiro Miyaji, Eisuke Isobe
2020 IEEJ Journal of Industry Applications  
The speed profiles based on this scheduling were installed on the ATO system, and experiments were carried out on track.  ...  This paper shows an additional method for energy saving by optimizing running time scheduling.  ...  Based Verification of Optimized Energy-Saving Train Scheduling Utilizing Automatic Train Operation System Shoichiro Watanabe et al. Table 2 .  ... 
doi:10.1541/ieejjia.9.193 fatcat:swimr5knrvbbzb3jvcwtydgm74

Modelling, Verification and Synthesis of Two-Tier Hierarchical Fixed-Priority Preemptive Scheduling

Mikael Åsberg, Paul Pettersson, Thomas Nolte
2011 2011 23rd Euromicro Conference on Real-Time Systems  
We model a hierarchically scheduled system using task automata, and we conduct verification with model checking using the Times tool.  ...  However, these benefits rely on the assumption that the scheduler itself schedules applications correctly according to the scheduling parameters and the chosen scheduling policy.  ...  We ran three different task/server systems (system 1, 2 and 3) during the verification of our scheduler properties. The three systems are presented in Table III , IV and V.  ... 
doi:10.1109/ecrts.2011.24 dblp:conf/ecrts/AsbergPN11 fatcat:ckguozefqrbw3ip4xvyvewfjxa

Static scheduling of multidomain circuits for fast functional verification

M. Kudlugi, R. Tessier
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Index Terms-Asynchronous circuits, FPGA-based emulation, functional verification, static scheduling.  ...  This paper presents new scheduling and synchronization techniques to support accurate mapping of designs with multiple asynchronous clocks to parallel verification hardware.  ...  Verification Software Flow Although individual systems may differ in implementation, design mapping similarities exist across many parallel verification systems.  ... 
doi:10.1109/tcad.2002.804086 fatcat:owoc5agfwjg5nicdstivbbnw3y

Automatic formal verification for scheduled VLIW code

Xiushan Feng, Alan J. Hu
2002 Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02  
VLIW processors are attractive for many embedded applications, but VLIW code scheduling, whether by hand or by compiler, is extremely challenging.  ...  In this paper, I extend previous work on automated verification of low-level software to handle the complexity of modern, aggressive VLIW designs, e.g., the exposed parallelism, pipelining, and resource  ...  In an actual system, the program which visits an invalid address will report an error and exit.  ... 
doi:10.1145/513829.513844 dblp:conf/lctrts/FengH02 fatcat:cgw473q6rbbgvlbczahsn2q734

An experiment in using RT-LOTOS for the formal specification and verification of a distributed scheduling algorithm in a nuclear power plant monitoring system [chapter]

L. Andriantsiferana, J.-P. Courtiat, R. C. Oliveira, L. Picci
1997 Formal Description Techniques and Protocol Specification, Testing and Verification  
More specifically, the experiment is devoted to the formal specification and verification of the distributed scheduling algorithm managing the hot redundancy between the two computers composing the system  ...  The main motivation behind the experiment was to get a better understanding of the fault-tolerant features of the scheduling algorithm by means of both simulation and formal verification.  ...  Validation of the scheduling algorithm This section presents some results related to the simulation and verification of the monitoring system scheduling algorithm.  ... 
doi:10.1007/978-0-387-35271-8_27 fatcat:zcibsu3hhrbblj2zgxbmkihtbq

A Hybrid Machine Learning and Schedulability Analysis Method for the Verification of TSN Networks

Tieu Long Mai, Nicolas Navet, Jorn Migge
2019 2019 15th IEEE International Workshop on Factory Communication Systems (WFCS)  
In this hybrid verification strategy, the clear-cut decisions are taken by ML, while the more difficult ones are taken by a conventional schedulability analysis.  ...  A disadvantage of ML-based timing verification with respect to schedulability analysis is the possibility of "false positives": configurations deemed feasible while they are not.  ...  To support these new use-cases, we need techniques like proposed in this paper that help speed up the timing verification of critical communication systems.  ... 
doi:10.1109/wfcs.2019.8757948 dblp:conf/wfcs/MaiNM19 fatcat:kreu7rq635f27ang37kq5dntau
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