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Scenario-based verification of real-time systems using Uppaal

Shuhao Li, Sandie Balaguer, Alexandre David, Kim G. Larsen, Brian Nielsen, Saulius Pusinskas
2010 Formal methods in system design  
This article proposes two approaches to tool-supported automatic verification of dense real-time systems against scenario-based requirements, where a system is modeled as a network of timed automata (TAs  ...  " approach, and then reduce the problems of scenario-based verification also to CTL real-time model checking problems.  ...  Thanks are also due to Itai Segall for useful discussions and for pointing out an error in an earlier version of the "one-TA-per-instance line" translation.  ... 
doi:10.1007/s10703-010-0103-z fatcat:b4wdli44bzborkkbikw3skcioy

Evaluating On-line Model Checking in UPPAAL-SMC using a Laser Tracheotomy Case Study

Xintao Ma, Jonas Rinast, Sibylle Schupp, Dieter Gollmann, Marc Herbstritt
2014 Workshop on Medical Cyber-Physical Systems  
Development of automatic on-line model checking relies on the precision of the prediction and real-time capabilities as real-time requirements must be met.  ...  On-line model checking is a variant of model checking that evaluates properties of a system concurrently while deployed, which allows overcoming limitations of inaccurate system models.  ...  We thank the anonymous reviewers of MedicalCPS 2014 for references to related work and comments that helped to improve the presentation.  ... 
doi:10.4230/oasics.mcps.2014.100 dblp:conf/mcps/MaRSG14 fatcat:4vil4uzfrncfhftoatsxm7jeny

Towards Formal Modeling and Verification of Resource Provisioning as a Service in Cloud

Wenbo Zhou, Lei Liu, Shuai Lu, Peng Zhang
2019 IEEE Access  
Then, client, service manager (including allocator, finish monitor, and time monitor), and resource service are modeled based on UPPAAL, respectively.  ...  Finally, we define some consistency properties that a service scenario needs to satisfy and formally verify whether our model satisfies these properties using the UPPAAL model checker.  ...  UPPAAL is a useful tool for analysis and verification of real-time and distributed systems. Zhou et al.  ... 
doi:10.1109/access.2019.2900473 fatcat:3326pkzw5fhpxjd2s52msxrrp4

UPPAAL in Practice: Quantitative Verification of a RapidIO Network [chapter]

Jiansheng Xing, Bart D. Theelen, Rom Langerak, Jaco van de Pol, Jan Tretmans, J. P. M. Voeten
2010 Lecture Notes in Computer Science  
A model checking approach has been proposed in our previous work which transforms the POOSL model into an UPPAAL model. However, such an approach only works for a fairly small system.  ...  Packet switched networks are widely used for interconnecting distributed computing platforms.  ...  Transformation from POOSL to UPPAAL UPPAAL is a tool for modeling, validation and verification of real-time systems.  ... 
doi:10.1007/978-3-642-16561-0_20 fatcat:cfgaop4knrb23cgjyzy6fhckly

HyComp: An SMT-Based Model Checker for Hybrid Systems [chapter]

Alessandro Cimatti, Alberto Griggio, Sergio Mover, Stefano Tonetta
2015 Lecture Notes in Computer Science  
HYCOMP relies on the encoding of the network into an infinite-state transition system, which can be analyzed using SMT-based verification techniques (e.g. BMC, K-induction, IC3).  ...  HYCOMP is a model checker for hybrid systems based on Satisfiability Modulo Theories (SMT). HYCOMP takes as input networks of hybrid automata specified using the HyDI symbolic language.  ...  The tool features an expressive input language and a rich set of functionalities, such as verification of invariant and LTL properties, verification of scenario specifications and parameter synthesis.  ... 
doi:10.1007/978-3-662-46681-0_4 fatcat:5dhashzxe5el5mwqljdcafkfqy

A Framework for Composition, Verification and Real-Time Performance of Multimedia Interactive Scenarios

Jaime Arias, Myriam Desainte-Catherine, Camilo Rueda
2015 2015 15th International Conference on Application of Concurrency to System Design  
ACKNOWLEDGMENT We thank the anonymous reviewers for their detailed comments that helped us to improve this paper.  ...  Timed Automata and UPPAAL Timed Automata (TA) [8] is a formalism for modelling and verification of real-time systems.  ...  In this paper, we present a timed automata (TA) [8] based framework to address the challenges in the modelling, verification and real-time performance of multimedia interactive scenarios.  ... 
doi:10.1109/acsd.2015.8 dblp:conf/acsd/AriasDR15 fatcat:dn7ohmiayrhwbo2m5ghpytrgpy

Integrating UML and UPPAAL for designing, specifying and verifying component-based real-time systems

André L. N. Muniz, Aline M. S. Andrade, George Lima
2009 Innovations in Systems and Software Engineering  
We demonstrate the overall process of our approach, from system design to verification, using a simple but real application, used in train control systems.  ...  A new tool for integrating formal methods, particularly model checking, in the development process of component-based real-time systems specified in UML is proposed.  ...  component-based real-time systems.  ... 
doi:10.1007/s11334-009-0103-6 fatcat:o3q6ndw4ajddjgkv63tedfioou

Cost Analysis for Embedded Systems: Experiments with Priced Timed Automata

Tolga Ovatman, Aske W. Brekling, Michael R. Hansen
2010 Electronical Notes in Theoretical Computer Science  
In order to achieve this, a basic model is built using priced timed automata and some resource consumption scenarios are verified.  ...  In this paper, we consider simple models of embedded systems and the automated analysis about timing and memory access costs of those models.  ...  Uppaal Cora can then make verification based on a query given in the Uppaal Requirement Specification Language.  ... 
doi:10.1016/j.entcs.2010.06.006 fatcat:o4vrpbo56neahletcgid75e7ym

Formal Verification and Design of Smart Stick for Blind People

Ayesha Naveed
2020 Zenodo  
Researchers these days widely use formal verification to verify software and embedded systems. This paper is based on a smart stick (embedded system) designed for blind people.  ...  The system is tested under different scenarios in verification and validation software to confirm its authenticity.  ...  For design verification UPPAAL model checker [3] is used. It can verify systems in real time by modeling them as networks in timed automata i.e. automation based on set of clocks.  ... 
doi:10.5281/zenodo.5148252 fatcat:24nvp3islzdwjhkkim7xvgieqe

Role Based Multi-Agent System for E-Learning (MASeL)

Mustafa Hameed, Nadeem Akhtar, Malik Saad
2016 International Journal of Advanced Computer Science and Applications  
Timedautomata based model checker UPPAAL is used for the specification as well as verification of the e-learning system.  ...  We have proposed a role-based multi-agent system for e-learning. This multi-agent system is based on Agent-Group-Role (AGR) method.  ...  UPPAAL: Timed-based automata model of student asking question in IVC L. Scenario-3: Use of White-board by participants of IVC Fig. 6.  ... 
doi:10.14569/ijacsa.2016.070327 fatcat:2sgennn4gzcfrk3mlifxtzkg6i

Analysis of ATO System Operation Scenarios Based on UPPAAL and the Operational Design Domain

Zicong Meng, Tao Tang, Guodong Wei, Lei Yuan
2021 Electronics  
The article models and verifies the scenario of the linkage control of the door and platform door based on the UPPAAL tools and extracts the input and expected output of the system requirements of the  ...  This paper presents the operational design domain (ODD) of the high-speed railway ATO system and proposes a scenario analysis method based on the operational design domain to obtain the input conditions  ...  Introduction to the Verification Tool UPPAAL UPPAAL is a modeling and verification tool specifically for real-time systems.  ... 
doi:10.3390/electronics10040503 fatcat:cgylzndpgjcljmrrmzrmqkq3qu

Safety-Assured Formal Model-Driven Design of the Multifunction Vehicle Bus Controller [chapter]

Yu Jiang, Han Liu, Houbing Song, Hui Kong, Ming Gu, Jiaguang Sun, Lui Sha
2016 Lecture Notes in Computer Science  
With the help of Uppaal, we check and debug whether the timed automata satisfy the formulas or not.  ...  We set up a real platform with worldwide mostly used MVBC D113, and verify the correctness and the scalability of the synthesized MVBC chip more comprehensively.  ...  We use the second way, because it can be automatically accomplished by parsing and updating the XML file of the timed automata model, and the second isolation way is more closed to the real operation scenario  ... 
doi:10.1007/978-3-319-48989-6_47 fatcat:5whqnf6ewjecjbcg4nsk7ajr3q

Security verification for cyber-physical systems using model checking

Ching-Chieh Chan, Cheng-Zen Yang, Chin-Feng Fan
2021 IEEE Access  
modeling and verification of real-time systems.  ...  Therefore, a subset of timed computation tree logic provided by UPPAAL was used for the verification. B.  ...  Author Name: Preparation of Papers for IEEE Access (February 2021) [38] will be conducted, as the latter can model the continuous behavior more accurately.  ... 
doi:10.1109/access.2021.3081587 fatcat:mml2d22cgrgczpokc2bqpzpeoq

Vooduu: Verification of Object-Oriented Designs Using UPPAAL [chapter]

Karsten Diethers, Michaela Huhn
2004 Lecture Notes in Computer Science  
., it verifies automatically whether a family of UML statecharts modelling a system satisfies a set of communication and timing constraints given as UML sequence diagrams.  ...  The verification is performed by the model checker UPPAAL. The results are retranslated into sequence diagrams. Thus the formal verification machinery is mainly hidden from the user.  ...  field of real-time applications.  ... 
doi:10.1007/978-3-540-24730-2_10 fatcat:almzu7fwjzg4jnjqkwhlxg7lhq

Safety Assessment of the Reconfigurable Integrated Modular Avionics Based on STPA

Changxiao Zhao, Lei Dong, Hao Li, Peng Wang, Zhiguang Song
2021 International Journal of Aerospace Engineering  
To solve the problem of lack of effective management mechanism for the IMA system development and safety assessment, a safety analysis method based on STAMP/STPA and UPPAAL for IMA reconfiguration is proposed  ...  Finally, the accessibility analysis of the formal model is used to analyze UCAs and the corresponding loss scenarios.  ...  To solve these problems, the formal verification UPPAAL based on time automata is introduced considering that the IMA system is a real-time system with strict time constraints.  ... 
doi:10.1155/2021/8875872 fatcat:nkrijdmr3ve47eo4mbokqgltgy
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