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Scavenger: A New Last Level Cache Architecture with Global Block Priority

Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, Jose Martinez
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
In this paper, we present Scavenger, a new architecture for last-level caches.  ...  Scavenger divides the total storage budget into a conventional cache and a novel victim file architecture, which employs a skewed Bloom filter in conjunction with a pipelined priority heap to identify  ...  We thank Vijay Degalahal for helping us with HSPICE, and Jugash Chandarlapati for developing the leakage energy model.  ... 
doi:10.1109/micro.2007.4408273 fatcat:cgcf5aeekff7jcg5drqwpawvvi

Scavenger: A New Last Level Cache Architecture with Global Block Priority

Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, Jose Martinez
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
In this paper, we present Scavenger, a new architecture for last-level caches.  ...  Scavenger divides the total storage budget into a conventional cache and a novel victim file architecture, which employs a skewed Bloom filter in conjunction with a pipelined priority heap to identify  ...  We thank Vijay Degalahal for helping us with HSPICE, and Jugash Chandarlapati for developing the leakage energy model.  ... 
doi:10.1109/micro.2007.42 dblp:conf/micro/BasuKKCM07 fatcat:4wuxz6mqcjh4hhywwemfy2x26i

An event-driven multithreaded dynamic optimization framework

Weifeng Zhang, B. Calder, D.M. Tullsen
2005 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)  
In this paper we propose a new dynamic optimization framework called Trident.  ...  Concurrent with the program's execution, the framework uses hardware support to identify optimization opportunities, and uses spare threads on a multithreaded processor to perform dynamic optimizations  ...  This research was supported by NSF grants CNS-0311683 and CCF-0311710, and a grant from Intel.  ... 
doi:10.1109/pact.2005.7 dblp:conf/IEEEpact/ZhangCT05 fatcat:l33zx2j7cbaxzoe7cz4tty2h5a

The ZCache: Decoupling Ways and Associativity

Daniel Sanchez, Christos Kozyrakis
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
Finally, we perform detailed simulations of multithreaded and multiprogrammed workloads on a large-scale CMP with zcache as the last-level cache.  ...  Hits, the common case, require a single lookup, incurring the latency and energy costs of a cache with a very low number of ways.  ...  Daniel Sanchez was supported by a Hewlett-Packard Stanford School of Engineering Fellowship.  ... 
doi:10.1109/micro.2010.20 dblp:conf/micro/SanchezK10 fatcat:jzzfxxjvqzbrplktlge4d2pija

High-performance parallel graph reduction [chapter]

Simon L Peyton Jones, Chris Clack, Jon Salkild
1989 Lecture Notes in Computer Science  
If it is still too full. local nodes without global counterparts can be flushed out of the cache by allocating them as new nodes in the global heap.  ...  When a task is blocked, its stack is tidied up. flushed into global memory, and a pointer to the topmost segment is attached to the blocking node.  ... 
doi:10.1007/3540512845_40 fatcat:rhom626ekvap7kq3dnjqmapfsi

Adaptive line placement with theset balancing cache

Dyer Rolán, Basilio B. Fraguela, Ramón Doallo
2009 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42  
This new technique, called Set Balancing Cache or SBC, achieved an average reduction of 13% in the miss rate of ten benchmarks from the SPEC CPU2006 suite, resulting in an average IPC improvement of 5%  ...  In this paper we present a technique that aims to balance the pressure on the cache sets by detecting when it may be beneficial to associate sets, displacing lines from stressed sets to underutilized ones  ...  More recently, Scavenger [2] has been proposed, which unlike SBC is exclusively oriented to last level caches and partitions the cache in two halves.  ... 
doi:10.1145/1669112.1669178 dblp:conf/micro/RolanFD09 fatcat:q3isgacbsre6ldvfxreif6zwaq

Optimizing Compiler for the CELL Processor

A.E. Eichenberger, K. O'Brien, K. O'Brien, Peng Wu, Tong Chen, P.H. Oden, D.A. Prener, J.C. Shepherd, Byoungro So, Z. Sura, A. Wang, Tao Zhang (+2 others)
2005 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)  
This first generation CELL processor implements on a single chip a Power Architecture processor with two levels of cache, and eight attached streaming processors with their own local memories and globally  ...  Results indicate that significant speedup can be achieved with a high level of support from the compiler.  ...  The Power Processor Element (PPE) consists of a 64-bit, multi-threaded Power Architecture processor with two levels of on-chip cache. The cache preserves global coherence across the system.  ... 
doi:10.1109/pact.2005.33 dblp:conf/IEEEpact/EichenbergerOOWCOPSSSWZZG05 fatcat:e54xideiibbn7dp5tqsh34oxgq

Multitasking without comprimise

Grzegorz Czajkowski, Laurent Daynés
2001 Proceedings of the 16th ACM SIGPLAN conference on Object oriented programming, systems, languages, and applications - OOPSLA '01  
MVM demonstrates that multitasking in a safe language can be accomplished with a high degree of protection, without constraining the language, and with competitive performance characteristics.  ...  best-effort management of a portion of the heap space, and a transparent and automated mechanism for safe execution of user-level native code.  ...  The last chunk is called current eden, and new The ability to grow eden may postpone the need for a scavenge, letting more objects become garbage before a collection takes place.  ... 
doi:10.1145/504282.504292 dblp:conf/oopsla/CzajkowskiD01 fatcat:rd36q7g52ramllfhr2ao7qvbuq

Multitasking without compromise

Grzegorz Czajkowski, Laurent Daynàs
2012 SIGPLAN notices  
best-effort management of a portion of the heap space, and a transparent and automated mechanism for safe execution of user-level native code.  ...  MVM demonstrates that multitasking in a safe language can be accomplished with a high degree of protection, without constraining the language, and with competitive performance characteristics.  ...  The last chunk is called current eden, and new The ability to grow eden may postpone the need for a scavenge, letting more objects become garbage before a collection takes place.  ... 
doi:10.1145/2442776.2442785 fatcat:j7jid6norzcwjejkvhznfnjo2q

Concurrent Computing in the Many-core Era (Dagstuhl Seminar 15021)

Michael Philippsen, Pascal Felber, Michael L. Scott, J. Eliot B. Moss, Marc Herbstritt
2015 Dagstuhl Reports  
This seminar is a successor to Dagstuhl Seminars 08241 "Transactional memory: From implementation to application" and 12161 "Abstractions for scalable multicore computing", respectively held in June 2008  ...  The current seminar built on the previous seminars by notably (1) broadening the scope to concurrency beyond transactional memory and shared-memory multicores abstractions, (2) focusing on the new challenges  ...  i.e., with global communication.  ... 
doi:10.4230/dagrep.5.1.1 dblp:journals/dagstuhl-reports/PhilippsenFSM15 fatcat:owcmta65hzb5vmglwq3dwzbehy

Idletime scheduling with preemption intervals

Lars Eggert, Joseph D. Touch
2005 Proceedings of the twentieth ACM symposium on Operating systems principles - SOSP '05  
This paper presents the idletime scheduler; a generic, kernel-level mechanism for using idle resource capacity in the background without slowing down concurrent foreground use.  ...  A FreeBSD disk scheduler implementation maintains 80% of foreground read performance, while enabling concurrent background operations to reach 70% throughput.  ...  This can cause priority inversion, where a higher-priority request at a higher level must wait for the completion of a lowerpriority one at a lower level [16] .  ... 
doi:10.1145/1095810.1095835 dblp:conf/sosp/EggertT05 fatcat:5rxnv37okzfqjbqzpdpmbf6i4y

Idletime scheduling with preemption intervals

Lars Eggert, Joseph D. Touch
2005 ACM SIGOPS Operating Systems Review  
This paper presents the idletime scheduler; a generic, kernel-level mechanism for using idle resource capacity in the background without slowing down concurrent foreground use.  ...  A FreeBSD disk scheduler implementation maintains 80% of foreground read performance, while enabling concurrent background operations to reach 70% throughput.  ...  This can cause priority inversion, where a higher-priority request at a higher level must wait for the completion of a lowerpriority one at a lower level [16] .  ... 
doi:10.1145/1095809.1095835 fatcat:ezg2pmkltjeslhe5w4by2uulwa

Efficient Master/Worker Parallel Discrete Event Simulation

Alfred Park, Ric Fujimoto
2009 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation  
I feel I have learned a great deal not only from his advisement and expertise but also through the exposure to a variety of projects that I was able to participate in.  ...  It has truly been an honor and a blessing to perform research under the supervision of one of the pioneers in the parallel and distributed simulation field.  ...  on the language and machine architecture levels.  ... 
doi:10.1109/pads.2009.9 dblp:conf/pads/ParkF09 fatcat:6aiga6uc6jdy5adfzhujiqab3a

Governor: Autonomic Throttling for Aggressive Idle Resource Scavenging

J.W. Strickland, V.W. Freeh, Xiaosong Ma, S.S. Vazhkudai
Second International Conference on Autonomic Computing (ICAC'05)  
at the same time, compared to a priority-based method.  ...  the impact below target levels.  ...  DE-AC05-00OR2275 with UT-Battelle, LLC and Xiaosong Ma's joint appointment between NCSU and ORNL.  ... 
doi:10.1109/icac.2005.31 dblp:conf/icac/StricklandFMV05 fatcat:7l7tzquz7rdntangw2bhemzsia

Minos—the design and implementation of an embedded real-time operating system with a perspective of fault tolerance

Thomas Kaegi-Trachsel, Juerg Gutknecht
2008 International Multiconference on Computer Science and Information Technology  
We introduce fault tolerance aspects in software by the concept of a very fast reboot procedure and by an error correcting flight data memory (FDM).  ...  This paper describes the design and implementation of a small real time operating system (OS) called Minos and its application in an onboard active safety project for General Aviation.  ...  A flight index in turn points to the first and the last header block of the corresponding flight.  ... 
doi:10.1109/imcsit.2008.4747312 dblp:conf/imcsit/Kaegi-TrachselG08 fatcat:j2jm5kchsbdjlpxlfwi52esmdy
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