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Survey of VLSI Test Data Compression Methods
2000
Nirma University Journal of Engineering and Technology
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Still there is a great need and scope for further reduction in test data volume. This reduction may be lossy for output side test data but must be lossless for input side test data. ...
The basic goal here is to prepare survey on current methodologies applied for test data compression and prepare a platform for further development in this avenue. ...
Test vector compression schemes fall broadly into three categories [1] : 1) Code-based schemes use data compression codes to encode test cubes. 2) Linear-decompression-based schemes decompress the data ...
doaj:660d7f3242e44a6e96e8c5ad55b4ef32
fatcat:perk7hup2fhxrmlvd2hiffhvku
Compression-Friendly Low Power Test Application Based on Scan Slices Reusing
2016
JSTS Journal of Semiconductor Technology and Science
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This paper presents a compression-friendly low power test scheme in EDT environment. ...
The proposed approach exploits scan slices reusing to reduce the switching activity during shifting for test scheme based on linear decompressor. ...
COMPRESSION-FRIENDLY LOW POWER TEST APPLICATION SCHEME
Proposed Test Architecture The scan-based hardware implementing for the proposed scheme is shown in Fig. 2 . ...
doi:10.5573/jsts.2016.16.4.463
fatcat:6a3imw4cvra7vdlrvrws7n3tiq
A scan disabling-based BAST scheme for test cost and test power reduction
2012
IEICE Electronics Express
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This paper proposes a novel scan disabling-based BIST-Aided Scan Test (BAST) scheme to reduce test data volume and test power. ...
Experimental results show the proposed scheme achieves a higher compression gain and lower test power than previous low-cost schemes for cases where the number of specified bits in the test set is relatively ...
Circuit name N No. of bits in T D Care-bit rate, r(%) Compression gain Shift-in power Test cost reduction vs [8] (%) Test cost reduction vs [1] (%) Power reduction vs [8] (%) Power reduction vs [1] (%) ...
doi:10.1587/elex.9.111
fatcat:kicdd4mravgnznbxqvkex3zvm4
A scan disabling-based BAST scheme for test cost reduction
2011
IEICE Electronics Express
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This paper proposes a scan disabling-based BIST-aided scan test (BAST) scheme. In this scheme, a pseudo-random pattern generator (PRPG) generates test vector for each slice in multiple scan chains. ...
An automatic test equipment (ATE) only needs to store the control signals instead of test data. ...
Existing test data compression methods mainly include four categories: non-linear code-based [1, 2] , broadcast-based [3, 4] , linear decompression-based [5, 6] and BIST-aided [7, 8] scan test schemes ...
doi:10.1587/elex.8.1367
fatcat:citsxozwpfezxeku7fopz6nncu
Test Data Compression with Alternating Equal-Run-Length Coding
2018
International Journal of Engineering & Technology
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This paper presents a new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing. ...
The AERL achieves up to 82.05 % of compression ratio as well as up to 39.81% and 93.20 % of peak and average-power transitions in scan-in mode during IC testing. ...
A technique for simultaneous reduction of both test data volume and test power named linear decompressor based test compression were presented in [8] . ...
doi:10.14419/ijet.v7i4.10.27925
fatcat:z4hk36ndevf7xejktcmzeshjka
On capture power-aware test data compression for scan-based testing
2008
2008 IEEE/ACM International Conference on Computer-Aided Design
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With given test cubes in scan-based testing, the "don't-care" bits can be exploited for test data compression and/or test power reduction. ...
In this paper, we propose a novel capture power-aware test compression scheme that is able to keep scan capture power under a safe limit with little loss in test compression ratio. ...
nonlinear code-based schemes that use data compression codes to encode test cubes; (ii) linear decompressor-based schemes that decompress the data using linear operations (e.g., XOR network and/or linear ...
doi:10.1109/iccad.2008.4681553
dblp:conf/iccad/LiLZHLX08
fatcat:ybh6d4rcpzfm3jeecrgbl25wo4
On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes
2010
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Our approach also supports multiple scan chains. Index Terms-Compression, DFT, low power, scan chain, test data volume. ...
The proposed schemes and techniques are based on the selective test pattern compression, they can reduce considerable shift-in power by skipping the switching signal passing through long scan chains. ...
SELECTIVE PATTERN COMPRESSION FOR POWER AND TEST DATA REDUCTION We have proposed two schemes using compression techniques to reduce test data and power. ...
doi:10.1109/tvlsi.2009.2021061
fatcat:lbkyegvrrnglfczcnmzqcbs23e
Low Power Estimation on Test Compression Technique for SoC based Design
2015
Indian Journal of Science and Technology
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Test power dissipation is one of the major challenging task in System on Chip (SoC). The objective of the paper is to reduce the power consumption during testing in VLSI testing field. ...
This paper analyzes the test power consumption for the test data to get the low power consumption by using switching activity. ...
Linear decompression, broadcast scan based and code based schemes are some schemes reduces the volume of test data. ...
doi:10.17485/ijst/2015/v8i14/61848
fatcat:m3zbk7v6m5clrbkave3rlybyqu
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment
2009
2009 Design, Automation & Test in Europe Conference & Exhibition
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In this work, we propose a generic framework for reducing scan capture power in test compression environment. ...
Various test data compression (TDC) schemes and low-power X-filling techniques were proposed to address the above problems. ...
Acknowledgements This work was supported in part by the General Research ...
doi:10.1109/date.2009.5090899
dblp:conf/date/LiuX09a
fatcat:pckyej2ljjanfih3hmkvsos2pa
Test volume and application time reduction through scan chain concealment
2001
Proceedings of the 38th conference on Design automation - DAC '01
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A test pattern compression scheme is proposed in order to reduce test data volume and application time. ...
While the number of virtual scan chains visible to the ATE is kept small, the number of internal scan chains driven by the decompressed pattern sequence can be significantly increased. ...
A number of schemes have been proposed for test data volume reduction of scan-based deterministic test by improving the effectiveness of test compaction [2, 4, 13, 14, 17] and compression schemes [7 ...
doi:10.1145/378239.378388
dblp:conf/dac/BayraktarogluO01
fatcat:gjhy3dsnlbafjaty4big4oketa
A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment
2008
Journal of electronic testing
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In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus ...
in the low power testing scheme can reduce the test volume size. ...
For test data reduction, a new test compression scheme using LFSR reseeding is proposed. ...
doi:10.1007/s10836-008-5062-6
fatcat:ldxkolekujd5tgbdbop5ebbufy
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design
2007
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. ...
The scheme utilizes a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. ...
Scan-in Power Reduction Analysis In this section, it is to investigate the test power reduction of this scheme. ...
doi:10.1109/tvlsi.2007.899232
fatcat:f7sdiftosvge3nl6lmmxwu7c5y
Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures
2016
IEICE transactions on information and systems
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Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. ...
Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%. ...
This work was partially supported by JSPS KAKENHI Grant-in-Aid for Scientific Research (B) #25280016 and JSPS KAKENHI Grant-in-Aid for Scientific Research on Innovative Areas #15K12003. ...
doi:10.1587/transinf.2015edp7289
fatcat:w4kog5rxk5c33ig6zeogwjyoeq
QC-Fill: An X-Fill method for quick-and-cool scan test
2009
2009 Design, Automation & Test in Europe Conference & Exhibition
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In this paper, we present an X-Fill (QC-Fill) method for not only slashing the test time but also reducing the test power (including both capture power and shifting power). ...
QC-Fill is independent of the ATPG patterns and does not require any area-overhead since it can directly operate on an existing scan architecture incorporating test compression. ...
ACKNOWLEDGEMENTS We are grateful to CIC (Chip Implementation Center) [27] , Taiwan, for their help in providing the needed commercial tools, including TetraMAX, Verilog-XL, and PrimePower used in our ...
doi:10.1109/date.2009.5090835
dblp:conf/date/TzengH09
fatcat:kpq3hauzsna2phnmhy7rzpmyum
An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR
2008
Journal of electronic testing
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Keywords Linear feedback shift register . Built-in self-test . ...
A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. ...
In [5] , a low power scheme based on scan slice overlapping has been introduced. But these schemes do not consider peak power reduction. ...
doi:10.1007/s10836-008-5077-z
fatcat:kvozjeopjrbl5dns6rvm4ueq4u
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