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Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core Systems

Maximilien Dupont de Dinechin, Matheus Schuh, Matthieu Moy, Claire Maiza
2020 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
In RTNS 2016, Rihani et al. [7] proposed an algorithm to compute the impact of interference on memory accesses on the timing of a task graph.  ...  Since we target many-core platforms with tens or hundreds of cores, applications likely to exploit the parallelism of these platforms are too large to be handled by this algorithm in reasonable time.  ...  Such a slowdown is called interference. In [5] a framework to develop time-predictable real-time systems for many-core architectures is introduced.  ... 
doi:10.23919/date48585.2020.9116460 dblp:conf/date/DinechinSMM20 fatcat:gu7tqyeajjabbiubo2rhvqmvpi

parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

T. Ungerer, C. Bradatsch, M. Gerdes, F. Kluge, R. Jahr, J. Mische, J. Fernandes, P.G. Zaykov, Z. Petrov, B. Boddeker, S. Kehr, H. Regler (+16 others)
2013 2013 Euromicro Conference on Digital System Design  
We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores  ...  Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion.  ...  ACKNOWLEDGMENT The research leading to these results has received funding from the European Union Seventh Framework Programme under grant agreement no. 287519 (parMERASA).  ... 
doi:10.1109/dsd.2013.46 dblp:conf/dsd/UngererBGKJMFZPBKRHROCBSBLGQPACURP13 fatcat:sc4uy2gpavcgtgj4gz3wxe3oym

Dynamic budgeting for settling DRAM contention of co-running hard and soft real-time tasks

Jonas Flodin, Kai Lampka, Wang Yi
2014 Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems (SIES 2014)  
This paper presents a scheme for controlling the sharing of main memory among cores, respectively the concurrently executing real-time tasks.  ...  With multiple real-time tasks concurrently competing for the access to the memory, the main memory can easily become the Achilles heel for the timing correctness of the tasks.  ...  hard real-time periodic task would miss its deadline due to interference on the memory bus.  ... 
doi:10.1109/sies.2014.6871199 dblp:conf/sies/FlodinLY14 fatcat:e37eiiok55cqzblnvr3cum3xka

Virtual Timing Isolation for Mixed-Criticality Systems

Johannes Freitag, Sascha Uhrig, Theo Ungerer, Marc Herbstritt
2018 Euromicro Conference on Real-Time Systems  
Commercial of the shelf multicore processors suffer from timing interferences between cores which complicates applying them in hard real-time systems like avionic applications.  ...  The basic idea is to apply a single-core execution based Worst Case Execution Time analysis and to accept a predefined slowdown during multicore execution.  ...  The target of future research will be enabling more than one core running hard real-time applications.  ... 
doi:10.4230/lipics.ecrts.2018.13 dblp:conf/ecrts/FreitagUU18 fatcat:4732xtv3pfaqjn556k5akn4o3e

ZSim

Daniel Sanchez, Christos Kozyrakis
2013 Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13  
We validate zsim against a real Westmere system on a wide variety of workloads, and find performance and microarchitectural events to be within a narrow range of the real system.  ...  Simulator performance scales well with both the number of modeled cores and the number of host cores.  ...  ACKNOWLEDGMENTS We thank Krishna Malladi for providing the initial version of the detailed memory controller.  ... 
doi:10.1145/2485922.2485963 dblp:conf/isca/SanchezK13 fatcat:iwrohdffnve2xmhuvx2nemwtta

ZSim

Daniel Sanchez, Christos Kozyrakis
2013 SIGARCH Computer Architecture News  
We validate zsim against a real Westmere system on a wide variety of workloads, and find performance and microarchitectural events to be within a narrow range of the real system.  ...  Simulator performance scales well with both the number of modeled cores and the number of host cores.  ...  ACKNOWLEDGMENTS We thank Krishna Malladi for providing the initial version of the detailed memory controller.  ... 
doi:10.1145/2508148.2485963 fatcat:7u3lcvfbgzgt5ijzbxp7zt25dq

Design of a time-predictable multicore processor: The T-CREST project

Martin Schoeberl
2018 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
This paper presents the T-CREST processor, a real-time multicore processor developed to be time-predictable and an easy target for static worst-case execution time analysis.  ...  We present how to achieve time-predictability at all levels of the architecture, from the processor pipeline, via a network-on-chip, up to the memory controller.  ...  RELATED WORK In the FP-7 project MERASA (Multi-Core Execution of Hard Real-Time Applications Supporting Analysability) [4] , the real-time processor CarCore was developed.  ... 
doi:10.23919/date.2018.8342138 dblp:conf/date/Schoeberl18a fatcat:mh42vr5rejdmvim7jujlqcrly4

Performance-controllable shared cache architecture for multi-core soft real-time systems

Myoungjun Lee, Soontae Kim
2013 2013 IEEE 31st International Conference on Computer Design (ICCD)  
However, tasks running on different cores increase interferences in the shared L2 cache, resulting in more deadline misses and, consequently, worse quality of real-time tasks.  ...  Multi-core processors with shared L2 caches can improve performance and integrate several functions of real-time systems on a single chip.  ...  In addition, for large scale multicore real-time systems, real-time priorities should be considered. We leave these as the future work. VI.  ... 
doi:10.1109/iccd.2013.6657097 dblp:conf/iccd/LeeK13 fatcat:apsypeovt5epxkh2kfr754zbaa

Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems [article]

Heechul Yun
2014 arXiv   pre-print
In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time.  ...  To minimize interference, we focus on LLC and DRAM bank partitioned systems. Based on the model, we propose an analysis that computes a safe upper bound for the worst-case memory interference delay.  ...  While these proposals are valuable, especially for hard real-time systems, they are not available in COTS systems.  ... 
arXiv:1407.7448v1 fatcat:u5o6nq3kwrdc5b3upgrg7lom24

Impact of Resource Sharing on Performance and Performance Prediction: A Survey [chapter]

Andreas Abel, Florian Benz, Johannes Doerfert, Barbara Dörr, Sebastian Hahn, Florian Haupenthal, Michael Jacobs, Amir H. Moin, Jan Reineke, Bernhard Schommer, Reinhard Wilhelm
2013 Lecture Notes in Computer Science  
It may severely reduce the performance of tasks executed on the cores, and it increases the complexity of timing analysis and/or decreases the precision of its results.  ...  Multi-core processors are increasingly considered as execution platforms for embedded systems because of their good performance/energy ratio.  ...  Much less has been done in the context of hard real-time systems.  ... 
doi:10.1007/978-3-642-40184-8_3 fatcat:vltmy7q5xbdthgtszl3gxn2x3q

Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems [article]

Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich
2019 arXiv   pre-print
Composable many-core systems enable the independent development and analysis of applications which will be executed on a shared platform where the mix of concurrently executed applications may change dynamically  ...  S.o.t.a. composable many-core systems are developed based on a fixed isolation scheme that is exclusively applied to every resource in every mapping of every application and use a timing analysis tailored  ...  Composability is particularly crucial for the development of dynamic many-core systems with variable workloads and hard real-time requirements.  ... 
arXiv:1905.13503v3 fatcat:lmjvwycfhfhlpn427c7qtxrzsm

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

Claire Maiza, Hamza Rihani, Juan M. Rivas, Joël Goossens, Sebastian Altmeyer, Robert I. Davis
2019 ACM Computing Surveys  
This survey provides an overview of the scientiic literature on timing veriication techniques for multi-core real-time systems.  ...  The survey highlights the key issues involved in providing guarantees of timing correctness for multi-core systems.  ...  research on analysis of NoCs.  ... 
doi:10.1145/3323212 fatcat:mn6xmduiyjfgzhemn5s2lmfgje

Identifying the sources of unpredictability in COTS-based multicore systems

Dakshina Dasari, Benny Akesson, Vincent Nelis, Muhammad Ali Awan, Stefan M. Petters
2013 2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES)  
Many of these embedded applications have real-timerequirements and real-time system designers must be ableassess them for their predictability and provide guarantees (atdesign time) that they deliver the  ...  We explore someof the existing work in timing analysis with respect to thesefeatures, identify their limitations, and present some unaddressedissues that must be dealt with to ensure safe deployment of  ...  In contrast, the key requirement for most hard real-time systems are platforms that are predictable and amenable to easier timing analysis.  ... 
doi:10.1109/sies.2013.6601469 dblp:conf/sies/DasariANAP13 fatcat:dg5rkpigebce7fkmpmbzry3fhm

Rethinking memory system design for data-intensive computing

Onur Mutlu
2015 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
X) Hardware/software manage data allocation and movement to achieve the best of multiple technologies An Orthogonal Issue: Memory Interference Main Memory 20 Core Core Core Core Cores  ...   Low-cost system-level tolerance of memory errors   Cai+, "Error Analysis and Retention-Aware Error Management for NAND Flash Memory," Intel Technology Journal 2013.  ... 
doi:10.1109/samos.2015.7363650 dblp:conf/samos/Mutlu15 fatcat:fc5a6u4sinhotaibqt6bsull2a

Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems

Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich, Michael Wagner
2019 Euromicro Conference on Real-Time Systems  
Experimental results demonstrate that, for a variety of real-time applications and many-core platforms, the proposed approach achieves an improvement of up to 67% in the quality of delivered mappings compared  ...  State-of-the-art composable many-core systems are developed based on a fixed isolation scheme that is exclusively applied to every resource in every mapping of every application and use a timing analysis  ...  Composability is particularly crucial for the development of dynamic many-core systems with variable workloads and hard real-time requirements.  ... 
doi:10.4230/lipics.ecrts.2019.12 dblp:conf/ecrts/PourmohseniSWT19 fatcat:ywc7wroq6neuhj43pa3eb36k3i
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