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Low Power and Energy Efficient Asynchronous Design

Peter A. Beerel, Marly E. Roncken
2007 Journal of Low Power Electronics  
This paper surveys the most promising low-power and energy-efficient asynchronous design techniques that can lead to substantial advantages over synchronous counterparts.  ...  Our discussions cover macro-architectural, micro-architectural, and circuit-level differences between asynchronous and synchronous implementations in a wide range of designs, applications, and domains  ...  We also thank Ivan Sutherland for helping us use the terms "energy" and "power" consistently, and for accepting-to his regret-our use of "open" and "closed" for latches.  ... 
doi:10.1166/jolpe.2007.138 fatcat:erlvur724ngp7bzbuluf2yn3se

Asynchronous Design—Part 1: Overview and Recent Advances

Steven M. Nowick, Montek Singh
2015 IEEE design & test  
As a recent example, an asynchronous NoC switch architecture, 9 using single-rail bundled data and two-phase communication, obtained a 45% reduction in average energy-per-packet and 71% area reduction  ...  Interestingly, dynamic logic is an especially good match for asynchronous pipelines.  ...  technologies, energy-efficient graphics, and image sensing hardware.  ... 
doi:10.1109/mdat.2015.2413759 fatcat:g5qkrrrdujdkld6fsx3fhyrem4

Aggressive Slack Recycling via Transparent Pipelines

Gokul Subramanian Ravi, Mikko H. Lipasti
2018 Proceedings of the International Symposium on Low Power Electronics and Design - ISLPED '18  
To combat this, we propose Aggressive Slack Recycling via Transparent Pipelines.  ...  Our proposal performs timing speculation while allowing data to flow asynchronously via transparent latches, between synchronous boundaries.  ...  To leverage the benefits of asynchronous solutions within the synchronous (pipelined) computing realm, we propose Aggressive Slack Recycling via Transparent Pipelines: 1 Simple "asynchronous" execution  ... 
doi:10.1145/3218603.3218623 dblp:conf/islped/RaviL18 fatcat:xp3wji3xbjgf5h5vw4vvocj2wu

Bandwidth optimization in asynchronous NoCs by customizing link wire length

Junbok You, Daniel Gebhardt, Kenneth S. Stevens
2010 2010 IEEE International Conference on Computer Design  
Energy and latency characteristics of an asynchronous NoC are compared to a similarly-designed synchronous NoC.  ...  Available bandwidth on an asynchronous NoC link will also vary depending on the wire length between sender and receiver.  ...  The complexity of an asynchronous pipeline latch is less than that of a router. This results in higher operating frequency of the pipeline latches allowing a higher bandwidth on repeated segments.  ... 
doi:10.1109/iccd.2010.5647660 dblp:conf/iccd/YouGS10 fatcat:qakkrrzltrdltdj4jx7l44pklq

Neural spiking dynamics in asynchronous digital circuits

Nabil Imam, Kyle Wecker, Jonathan Tse, Robert Karmazin, Rajit Manohar
2013 The 2013 International Joint Conference on Neural Networks (IJCNN)  
A digital implementation results in stable, reliable and highly programmable circuits, while an asynchronous design style leads to energy-efficient clockless neurons and their networks that mimic the event-driven  ...  In 65 nm CMOS technology at 1 V operating voltage and a 16-bit word length, our neuron can update its state 11,600 times per millisecond while consuming 0.5 nJ per update.  ...  Our asynchronous design methodology is well-suited for the counterflow pipeline implementation of the algorithm, and leads to an area and energy-efficient design.  ... 
doi:10.1109/ijcnn.2013.6706952 dblp:conf/ijcnn/ImamWTKM13 fatcat:js5txrg54beczc3suwa2bdibsi

The Amulet chips: Architectural development for asynchronous microprocessors

J.D. Garside, S.B. Furber, S. Temple, J.V. Woods
2009 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)  
In addition deadlocks, an ever-present danger in asynchronous systems, are discussed and means of preempting them presented.  ...  their low-energy and wide spectrum electromagnetic emission -useful in wireless applications.  ...  The energy per operation of the Amulet processors were close to equivalent to their synchronous counterparts.  ... 
doi:10.1109/icecs.2009.5411006 dblp:conf/icecsys/GarsideFTW09 fatcat:rptz35hfbfc5rdznpbtsirvwbi

Toward a multiple clock/voltage island design style for power-aware processors

E. Talpes, D. Marculescu
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Such a design style fits nicely with the recently proposed concept of voltage islands that, in addition, can potentially enable fine-grain dynamic power management by simultaneous voltage and frequency scaling  ...  However, due to an increased execution time, even though the power per cycle is significantly improved, the total energy per task required by the GALS processor is only slightly decreased (Fig. 7) .  ...  This is mainly manifested via nonuniform resource usage, as well as bursty communication patterns among various parts of the pipeline.  ... 
doi:10.1109/tvlsi.2005.844305 fatcat:7azarbcc4rbzfbimlassepc5ki

High Performance Asynchronous Pipelined QDI Templates for DCT Matrix-vector Multiplication

D. Jayanthi, M. Rajaram
2012 International Journal of Computer Applications  
The mass application of asynchronous design has been an elusive goal for academic researchers while recent advances are promising.  ...  Our proposed asynchronous design yields 35% higher average throughput and negligible energy overhead compared with conventional synchronous design.  ...  Table 1 exhibits average power, cycle time, and energy per cycle.  ... 
doi:10.5120/8850-3131 fatcat:q2h2jp3duzgw3hvouy34u5zbpu

An Asynchronous Floating-Point Multiplier

Basit Riaz Sheikh, Rajit Manohar
2012 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems  
When compared against a custom synchronous FPM design, our asynchronous FPM consumes 3X less energy per operation while operating at 2.3X higher throughput.  ...  A higher radix array multiplier design with operand-dependent carrypropagation adder and low handshake overhead pipeline design is presented, which yields significant energy savings while preserving the  ...  For frequently occurring zero input operations in sparse matrix applications, our proposed FPM yields an even lower latency and energy per operation.  ... 
doi:10.1109/async.2012.19 dblp:conf/async/SheikhM12 fatcat:t5hagnecpndotc3sqzcwk37ksm

Power efficiency of voltage scaling in multiple clock, multiple voltage cores

Anoop Iyer, Diana Marculescu
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
Our results show that MCDV cores consume 22% less power at an average 12% performance loss.  ...  In this paper we study the effect of using a Globally Asynchronous Locally Synchronous (GALS) organization for a superscalar, out-of-order processor, both in terms of power and performance.  ...  Lemma 1 Assuming a linear pipeline organization (without feedback paths), the SCDV pipeline achieves better energy savings than the MCDV under the same slowdown factor per computation, if the switched  ... 
doi:10.1145/774572.774629 dblp:conf/iccad/IyerM02 fatcat:st2sjbppozghpgoxmqlxf6zu2y

Efficient adders for assistive devices

Mansi Jhamb, Gitanjali
2017 Engineering Science and Technology, an International Journal  
In this paper, we present a qualitative as well as a quantitative analysis of an asynchronous pipelined adder design with two latest computation completion sensing approaches based on Pseudo NMOS logic  ...  Since the adder is the most widely used component in all present day assistive devices, this analysis acts as a pointer for the application of asynchronous pipelined circuits with efficient Pseudo NMOS  ...  As observed from Table 2 , the asynchronous fine grain dynamic pipelined adder structure dissipates highest energy (per switching event) at vdd = 1.1 V when CSC1 was used for completion detection which  ... 
doi:10.1016/j.jestch.2016.09.007 fatcat:m5qxne6hpzbxzeedbxvfdh3lya

Big data challenges in simulation-based science

Manish Parashar
2014 Proceedings of the sixth international workshop on Data intensive distributed computing - DIDC '14  
Traditional Simulation -> Insight Pipelines Break Down • Traditional simulation -> insight pipeline: -Run large-scale simulations on large supercomputers -Dump data on parallel disk systems -Export data  ...  Goal • Enable parallel in-memory indexing and querying to support online query-driven data analysis for large scale scientific simulations Problems of traditional file-based approach • Parallel I/O operations  ... 
doi:10.1145/2608020.2612731 dblp:conf/hpdc/Parashar14 fatcat:f4a4iueobjgfdhsq7mfytlhs3i

A dynamically reconfigurable asynchronous processor

K.A. Fawaz, T. Arslan, S. Khawam, M. Muir, I. Nousias, I. Lindsay, A. Erdogan
2010 2010 IEEE 8th Symposium on Application Specific Processors (SASP)  
buffers 4.2 Synthesis of Asynchronous Operational cells Table 4 . 4 2: Comparing area, delay, power, and energy of different versions of an asynchronous operational cell (ADDCOMP).A datapath made  ...  Depending on the topology of the circuit, an operational cell would connect to other units via the programmable switch.The DRAP architecture uses a topology where each operational cell communicates with  ...  A 32-bit and an 18-bit version of each of the operational cell were designed for the DRAP evaluation.  ... 
doi:10.1109/sasp.2010.5521141 dblp:conf/sasp/FawazAKMNLE10 fatcat:zpsq3pfglvhmxm2issmepmnlue

Time for a "Greener" Internet

M. Baldi, Y. Ofek
2009 2009 IEEE International Conference on Communications Workshops  
Since a lot of the Internet traffic growth comes from predictable services (such as video) there is a huge potential for decreasing future Internet energy requirements by synchronizing the operation of  ...  It is anticipated that the Internet traffic will continue to grow exponentially for the foreseeable future, which will require ever-growing energy (electricity).  ...  Figure 2 : 2 Pipeline forwarding operation.  ... 
doi:10.1109/iccw.2009.5208036 fatcat:a66g4pz6r5gdrfzymbush5ieb4

Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2007 IEEE Journal of Solid-State Circuits  
The former portion pipelines the entire operation asynchronously within the processor and the latter portion executes the butterfly operations.  ...  Each data flow requires five pipeline stages: Memory Read, Scaling, Multiplications, Additions/Subtractions, and Write Back.  ...  He was an Assistant Professor in the School of Electrical and Electronics Engineering, NTU, from 1999 to 2005, and has been an Associate Professor at NTU since 2005.  ... 
doi:10.1109/jssc.2007.903039 fatcat:ongqhjegqrcs3gdavghkbf6xp4
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