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Scalable network virtualization using FPGAs
2010
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10
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Dynamic FPGA reconfiguration is supported to adapt to changing networking needs. System scalability is demonstrated for up to 15 virtual routers. ...
Recent virtual network implementations have shown the capability to implement multiple network data planes using a shared hardware substrate. ...
Two very recent efforts assess the use of FPGAs in virtual networking. ...
doi:10.1145/1723112.1723150
dblp:conf/fpga/UnnikrishnanVLDCGT10
fatcat:oif5axtbprc4rat5rhvzutweci
Reconfigurable Data Planes for Scalable Network Virtualization
2013
IEEE transactions on computers
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Recent advances in network virtualization advocate the use of field-programmable gate arrays (FPGAs) as flexible high performance alternatives to conventional host virtualization techniques. ...
The research described in this manuscript explores the implementation of a scalable heterogeneous network virtualization platform which integrates virtual data planes implemented in FPGAs with software ...
The FPGA compilation tools were generously donated by Xilinx Corporation. ...
doi:10.1109/tc.2012.155
fatcat:sq7xdztilrdadniplvkrxrcwyq
Building a Flexible and Scalable Virtual Hardware Data Plane
[chapter]
2012
Lecture Notes in Computer Science
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In this paper, using FPGA (Field Program Gate Array) and TCAM (Ternary Content Addressable Memory), we design and implement a virtual hardware data plane achieving high performance, flexibility and scalability ...
Network virtualization which enables the coexistence of multiple networks in shared infrastructure adds extra requirements on data plane of router. ...
Besides FPGA, there is a rising interest on using GPU for network processing. ...
doi:10.1007/978-3-642-30045-5_16
fatcat:yzbp6yuh5bfjhad337mfte2vwi
Power-efficient and scalable virtual router architecture on FPGA
2012
2012 International Conference on Reconfigurable Computing and FPGAs
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We propose a power-efficient scalable architecture for implementing router virtualization using the Virtualized Merged (VM) approach on Field-programmable Gate Array (FPGA). ...
Router virtualization alleviates these issues by allowing a single hardware router to serve packets from multiple networks. ...
This can become a severe bottleneck for scalability when increasing the number of virtual networks. ...
doi:10.1109/reconfig.2012.6416793
dblp:conf/reconfig/HariaGP12
fatcat:bectkbmytzbjbi4evmrrhvotjy
Towards On-the-Fly Incremental Updates for Virtualized Routers on FPGA
2011
2011 21st International Conference on Field Programmable Logic and Applications
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Node sharing is avoided by using a uniform data structure that results in a scalable solution for router virtualization. ...
In this paper, we propose a Field Programmable Gate Array (FPGA) based architecture for router virtualization that supports on-the-fly updates, while ensuring scalability and throughput requirements. ...
Recently, network virtualization has drawn a lot of attention from the networking community [4] , [5] , [11] . ...
doi:10.1109/fpl.2011.46
dblp:conf/fpl/GanegedaraLP11
fatcat:d5ncvl2lkng3bi5bifr24yc3di
Revisiting the High-Performance Reconfigurable Computing for Future Datacenters
2020
Future Internet
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This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication ...
The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. ...
CGRAs offer higher performance and scalability with lower power consumption, the very characteristics FPGAs are used for. ...
doi:10.3390/fi12040064
fatcat:zrt5ergxnvezlmltkbwgiixcm4
Fast scalable FPGA-based Network-on-Chip simulation models
2011
Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011)
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For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized time-multiplexed approach was used. ...
For smaller networks and simpler router configurations a directmapped approach was employed, where the network to be simulated was directly implemented on the FPGA. ...
direct-mapped design that laid out the entire simulated target network on the FPGA and ii) a virtualized time-multiplexed design used to efficiently simulate larger network configurations that would not ...
doi:10.1109/memcod.2011.5970513
dblp:conf/memocode/Papamichael11
fatcat:j4cpckjovjf6tgkerjplpmkhtq
Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures
2012
2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
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We address these shortcomings by designing a new FPGA board for multicore architecture prototyping, which explicitly targets scalability and cost-efficiency. ...
An effective practice that balances both targets well is to map the target architecture on FPGA platforms. ...
We would like to thank Xilinx for the donation of 64 Spartan-6 FPGA devices. ...
doi:10.1109/fccm.2012.20
dblp:conf/fccm/LyberisKLPTKPN12
fatcat:mbb47teopngapok6v5knrtctfa
Dynamically reconfigurable simulation platform for 3D NoC based on multi-FPGA
2015
IEICE Electronics Express
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The design method of RcEF3Ns employs a single FPGA to manage vertical transaction independently, supporting bus and network communication mechanism. ...
But there still exist some difficulties such as partition, scalability and so on. ...
The use of a high-speed inter-FPGA communication enhances the latency on 3D NoC. ...
doi:10.1587/elex.12.20150065
fatcat:p57br4tf2fbyzbh3xyf2nkkx7i
Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI
2011
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '11
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Therefore, many FPGAs are required to implement very large networks for use in real-world applications. ...
In this paper, we present a number of improvements to a virtualized FPGA architecture for RBMs. First, we take advantage of 16-bit arithmetic to pack larger networks onto a chip. ...
This type of application is the focus of the virtualized RBM design, and thus the limits on scalability will not affect the majority of use cases. ...
doi:10.1145/1950413.1950452
dblp:conf/fpga/LoC11
fatcat:5vjqo2xigngrzc4jp2d6dwrhaa
FPGA-based Router Virtualization: A Power Perspective
2012
2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
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Low power FPGA families are explored in this work to highlight the benefits of using such platforms in networking environments. ...
In this paper, we study the effect of router virtualization, from a power consumption perspective, on the widely used Field Programmable Gate Array (FPGA) platform. ...
Hence, the scalability of the separate virtualization approach dictated by the platform used. ...
doi:10.1109/ipdpsw.2012.44
dblp:conf/ipps/GanegedaraP12
fatcat:62kugvgowjgz7jaq32gahaj7mu
Unifying manycore and FPGA processing with the RUSH architecture
2011
2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
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As a result, data sharing and dynamic workload scheduling across heterogeneous architectures are often suboptimal and hindered by poor scalability. ...
However, for many applications, certain timing-critical tasks still require the performance efficiency of an FPGA co-processor. ...
FPGA-side libraries. A virtual tile on the FPGA is built from an IP block that defines the processing kernel and a lightweight interface to the physical network. ...
doi:10.1109/ahs.2011.5963950
dblp:conf/ahs/BeresiniRT11
fatcat:hfkqzjly5vccpilrfx54jgvnhy
From FPGA to Support Cloud to Cloud of FPGA: State of the Art
2019
International Journal of Reconfigurable Computing
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We present a survey of the cloud FPGA works that have been proposed to exploit the advantages of using FPGA in the cloud. ...
As more and more FPGA are being deployed in traditional cloud, it is appropriate to clarify what is the cloud FPGA and which drawbacks of using FPGA in local are resolved. ...
NARC [37] is a standalone network-attached FPGA board designed for high-performance computing and network applications. e board consists of a Xilinx FPGA and an ARM processor. e ARM processor is used ...
doi:10.1155/2019/8085461
fatcat:fnhvx3aqxzev3kqk7psmxkqine
From the Dynamic Lattice Liquid Algorithm to the Dedicated Parallel Computer – mDLL Machine
2018
Computational Methods in Science and Technology
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KDLL) were located in the nodes of a three-dimensional torus network and the device was scalable. ...
Despite some structural shortcomings, the mDLL machine was a prototype that has already been sufficiently tested to allow the technology used in it to be used to build a device with a number of 1 million ...
It turned out that the system of equations used for converting virtual spatial coordinates x, y, z operational cells implemented in FPGAs to their x s , y s , z s coordinates in the actual RCL network ...
doi:10.12921/cmst.2018.0000054
fatcat:cj7xtjtwrvcotlqjy7n2z4v7xq
SPADnet network modeling, simulation and emulation
2014
2014 19th IEEE-NPSS Real Time Conference
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Abstract-A complete simulation environment, designed to aid the SPADnet network design and to perform scalability studies, is presented in this work. ...
Two simulators, namely a coincidence network simulator and a data transfer simulator, designed to simulate two network channels, were optimized for speed and memory. ...
A detailed analysis performed using the presented simulators for various configurations of PET systems [2] has allowed us to demonstrate the network scalability to preclinical, clinical and to brain ...
doi:10.1109/rtc.2014.7097553
fatcat:7w6zegfz55gcxlkla535mgh64m
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