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Big biomedical image processing hardware acceleration: A case study for K-means and image filtering

Katayoun Neshatpour, Arezou Koohi, Farnoud Farahmand, Rajiv Joshi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun
2016 2016 IEEE International Symposium on Circuits and Systems (ISCAS)  
To address this challenge, in this paper, we introduce a scalable and efficient hardware acceleration method using low cost commodity FPGAs that is interfaced with a server architecture through a high  ...  FPGA-based hardware accelerating environment.  ...  To address this challenge, in this paper, we introduce a scalable and efficient hardware acceleration method using low cost commodity FPGAs that is interfaced with a server architecture through a high  ... 
doi:10.1109/iscas.2016.7527445 dblp:conf/iscas/NeshatpourKFJRS16 fatcat:ngueu6tyivhdviizxa7mcasx4a

High-level synthesizable dataflow MapReduce accelerator for FPGA-coupled data centers

Dionysios Diamantopoulos, Christoforos Kachris
2015 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
However, FPGAs have not been deployed in data centers due to the high programming complexity of hardware.  ...  FPGAs can be used to accelerate the processing of data and reduce significantly the power consumption.  ...  In [4] a MapReduce Framework on FPGA accelerated commodity hardware is presented where a cluster of worker nodes is designed for the MapReduce framework, and each worker node consists of commodity hardware  ... 
doi:10.1109/samos.2015.7363656 dblp:conf/samos/DiamantopoulosK15 fatcat:tg2h7ptl55cmfckegx2pqjxawi

Big data analytics on heterogeneous accelerator architectures

Katayoun Neshatpour, Avesta Sasan, Houman Homayoun
2016 Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES '16  
based language suited for interfacing with FPGA-based hardware accelerating environment.  ...  We present a full implementation of the HW+SW mappers on the Zynq FPGA platform.  ...  MARS [7] , a MapReduce framework on an NVIDIA G80 GPU and Cluster GPU MapReduce [8] are examples of the GPU-based accelerator platforms.  ... 
doi:10.1145/2968456.2976765 dblp:conf/codes/NeshatpourSH16 fatcat:yfmehx5ggzgczm7pqdl77tng7u

Heterogeneous Cloud Framework for Big Data Genome Sequencing

Chao Wang, Xi Li, Peng Chen, Aili Wang, Xuehai Zhou, Hong Yu
2015 IEEE/ACM Transactions on Computational Biology & Bioinformatics  
In this paper, we propose a novel FPGA-based acceleration solution with MapReduce framework on multiple hardware accelerators.  ...  Also, as a practical study, we have built a hardware prototype on the real Xilinx FPGA chip.  ...  Google uses this framework internally to execute thousands of MapReduce applications per day, processing petabytes of data, all on commodity hardware.  ... 
doi:10.1109/tcbb.2014.2351800 pmid:26357087 fatcat:52gw5e6o6jc5tefrr3xau3kdcm

Hadoop Extensions for Distributed Computing on Reconfigurable Active SSD Clusters

Abdulrahman Kaitoua, Hazem Hajj, Mazen A. R. Saghir, Hassan Artail, Haitham Akkary, Mariette Awad, Mageda Sharafeddine, Khaleel Mershad
2014 ACM Transactions on Architecture and Code Optimization (TACO)  
Our results show that for a hardware acceleration factor of 20×, compute-intensive workloads processing 153MB of data can run up to 11× faster than a standard Hadoop cluster.  ...  Using the Hadoop RASSD platform and network simulators, we validate our design and demonstrate its impact on performance for different workloads taken from Stanford's Phoenix MapReduce project.  ...  In Shan [2010] , the authors propose a framework for the MapReduce programming model on FPGAs.  ... 
doi:10.1145/2608199 fatcat:xlfenftdlndwlaqandq35bcehu

A survey on platforms for big data analytics

Dilpreet Singh, Chandan K Reddy
2014 Journal of Big Data  
Apache hadoop Apache Hadoop [6] is an open source framework for storing and processing large datasets using clusters of commodity hardware.  ...  frameworks such as MapReduce (explained in section "Apache hadoop").  ...  Authors' contributions DS worked on the preparation of the manuscript. He also worked on the pseudocodes presented in the paper.  ... 
doi:10.1186/s40537-014-0008-6 pmid:26191487 pmcid:PMC4505391 fatcat:uycfqkl5ljenlipwzhvodxnove

Energy-Efficient Big Data Analytics in Datacenters [chapter]

Farhad Mehdipour, Hamid Noori, Bahman Javadi
2016 Advances in Computers  
Netezza minimizes data movement by using innovative hardware acceleration.  ...  GPU and FPGA are the possible accelerators that can achieve higher performance and energy efficiency than CPUs on certain jobs.  ... 
doi:10.1016/bs.adcom.2015.10.002 fatcat:xpecmdmje5avvphkdrdnyv4fqi

ELASTIC CLOUD COMPUTING ARCHITECTURE AND SYSTEM FOR HETEROGENEOUS SPATIOTEMPORAL COMPUTING

X. Shi
2017 ISPRS Annals of the Photogrammetry, Remote Sensing and Spatial Information Sciences  
Now that a variety of hardware accelerators and computing platforms are available to improve the performance of geocomputation, different algorithms may have different behavior on different computing infrastructure  ...  Some are perfect for implementation on a cluster of graphics processing units (GPUs), while GPUs may not be useful on certain kind of spatiotemporal computation.  ...  Hadoop MapReduce is a software framework for easily writing applications which process big amounts of data inparallel on large clusters of commodity hardware in a reliable, fault-tolerant manner.  ... 
doi:10.5194/isprs-annals-iv-4-w2-115-2017 fatcat:3iij6pxybjbxno2524jbhbbea4

Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale

Muhuan Huang, Di Wu, Cody Hao Yu, Zhenman Fang, Matteo Interlandi, Tyson Condie, Jason Cong
2016 Proceedings of the Seventh ACM Symposium on Cloud Computing - SoCC '16  
Our Blaze runtime implements an FaaS framework to efficiently share FPGA accelerators among multiple heterogeneous threads on a single node, and extends Hadoop YARN with accelerator-centric scheduling  ...  With the emerging trend of FPGA-enabled datacenters, one key question is: How can we easily and efficiently deploy FPGA accelerators into state-of-the-art big data computing systems like Apache Spark [  ...  Domain-Specific Computing under the NSF InTrans Award CCF-1436827, funding from CDSC industrial partners including Baidu, Fujitsu Labs, Google, Huawei, Intel, IBM Research Almaden, and Mentor Graphics; C-FAR, one  ... 
doi:10.1145/2987550.2987569 pmid:28317049 pmcid:PMC5351886 dblp:conf/cloud/HuangWYFICC16 fatcat:5f6bnm6xxbfk3k5fv3sgqarftu

RETHINK big: European roadmap for hardware anc networking optimizations for big data

Gina Alioto, Paul Carpenter, Adrian Cristal, Osman Unsal, Marcus Leich, Christophe Avare
2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017  
Moreover, it presents coordinated technology development recommendations (focused on optimizations in networking and hardware) that would be in the best interest of European Big Data companies to undertake  ...  This paper discusses the results of the RETHINK big Project, a 2-year Collaborative Support Action funded by the European Commission in order to write the European Roadmap for Hardware and Networking optimizations  ...  ACKNOWLEDGMENT This project has received funding from the European Union's Seventh Framework Programme for research, technological development and demonstration under grant agreement n° 619788.  ... 
doi:10.23919/date.2017.7926969 dblp:conf/date/AliotoCCULA17 fatcat:gk4rhlw6mzemzmgkj3a4lqd3bi

On the inequality of the 3V's of Big Data Architectural Paradigms: A case for heterogeneity [article]

Todor Ivanov, Nikolaos Korfiatis, Roberto V. Zicari
2013 arXiv   pre-print
This paper contributes on the understanding of the Hadoop ecosystem from the perspective of different workloads and aims to help researchers and practitioners on the design of scalable platforms targeting  ...  Similar to other conjectures such as the CAP theorem 3V based architectures differ on their implementation.  ...  In (Shan et al. 2010) , the authors present a MapReduce framework (FPMR) implemented on FPGA that achieves 31.8x speedup compared to CPU-based software system.  ... 
arXiv:1311.0805v2 fatcat:yu7niwfs5fdx7nwe4vd7vtpkve

D4.1 Programming Language And Runtime System: Requirements

Hans Vandierendonck
2016 Zenodo  
The VINEYARD projects aims to achieve easy-to-use and transparent acceleration of data analytics.  ...  One of the components in the VINEYARD is the programming model and runtime system support, which is developed in Work Package 4.  ...  In this work a MapReduce framework on FPGA, which provides programming abstraction, hardware architecture, and basic building blocks to developers is presented.  ... 
doi:10.5281/zenodo.898162 fatcat:h4qoibk26vfzdao5badtj6fdie

Comparing the performance of clusters, Hadoop, and Active Disks on microarray correlation computations

J.A. Delmerico, N.A. Byrnes, A.E. Bruno, M.D. Jones, S.M. Gallo, V. Chaudhary
2009 2009 International Conference on High Performance Computing (HiPC)  
The Hadoop software framework is designed to enable data-intensive applications on cluster architectures, and offers significantly better scalability due to its distributed file system.  ...  Although the performance of these types of applications on a cluster can be improved by parallelization, storage hardware and network limitations restrict the scalability of an I/O-bound application such  ...  To accelerate the processing further, one can use special-purpose hardware to optimize certain kinds of operations.  ... 
doi:10.1109/hipc.2009.5433190 dblp:conf/hipc/DelmericoBBJGC09 fatcat:ftw5qcbi55dcfkj7xku5zfkoki

A Survey on Accelerated Mapreduce for Hadoop

Jyotindra Tiwari, Dr. Mahesh Pawar, Dr. Anjajana Pandey
2017 Oriental journal of computer science and technology  
It also supports distributed architecture where the data is stored across the cluster of commodity hardware.  ...  ranajoy Malakar et al., 2013 8 build a high performance system for image processing on heterogeneous devices by integrating CUDA acceleration into Hadoop framework.  ... 
doi:10.13005/ojcst/10.03.07 fatcat:b2y4foroavdirhf4ny3v2vabfa

CNNLab: a Novel Parallel Framework for Neural Networks using GPU and FPGA-a Practical Study with Trade-off Analysis [article]

Maohua Zhu, Liu Liu, Chao Wang, Yuan Xie
2016 arXiv   pre-print
To improve the performance and maintain the scalability, we present CNNLab, a novel deep learning framework using GPU and FPGA-based accelerators.  ...  Experimental results on the state-of-the-art Nvidia K40 GPU and Altera DE5 FPGA board demonstrate that the CNNLab can provide a universal framework with efficient support for diverse applications without  ...  FPGA and Hardware based Accelerators To overcome the power consumption issue of the GPU and Cloud based frameworks, many developers seek solutions at hardware level [16] , [17] , [18] .  ... 
arXiv:1606.06234v1 fatcat:en7acoahonb7beqrnxv553g46e
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