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The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

Abdelhakim Alali, Hasna Elmaaradi, Mohammed Khaldoun, Mohamed Sadik
2021 Indonesian Journal of Electrical Engineering and Informatics (IJEEI)  
Indeed, we have selected design methods of SoC (ESP4ML and HLS4ML, OpenESP, LiteX, RubyRTL, PyMTL, SysPy, PyRTL, DSSoC) and NoC networks on OCN chip (PyOCN) and in general on FPGA (PRGA, OpenFPGA, AnyHLS  ...  DS3 DS3 [14] (system-level domain-specific SoC simulation) is a system-level domain-specific SoC simulation platform.  ...  OpenESP OpenESP [11] is an open-source, tile-based platform for implementing SoCs. It is intended for applications that develop and enhance accelerators.  ... 
doi:10.52549/ijeei.v9i4.3243 fatcat:k76nmwodi5cfxk4c4hk3nojc7e

Pushing the Level of Abstraction of Digital System Design: a Survey on How to Program FPGAs

Emanuele Del Sozzo, Davide Conficconi, Alberto Zeni, Mirko Salaris, Donatella Sciuto, Marco D. Santambrogio
2022 ACM Computing Surveys  
Here, we survey three leading digital design abstractions: Hardware Description Languages (HDLs), High-Level Synthesis (HLS) tools, and Domain-Specific Languages (DSLs).  ...  , and infrastructure domains for DSLs.  ...  ACKNOWLEDGEMENTS The authors are grateful for feedbacks from Reviewers and NECSTLab members, with a particular mention to A. Damiani, A. Parravicini, E. D'Arnese, F. Carloni, F. Peverelli, and R.  ... 
doi:10.1145/3532989 fatcat:nsk5lwvt3vba5fbxmaj7sgpwru

Simpler, more efficient design

Borivoje Nikolic
2015 ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)  
Design of custom integrated circuits has become prohibitively expensive for many application domains.  ...  These principles are demonstrated on a design of a processor, based on an open-source instruction set architecture, with integrated switched-capacitor DC-DC converters implemented in 28nm FDSOI.  ...  Chisel is based on the Scala programming language, and is built by extending Scala.  ... 
doi:10.1109/esscirc.2015.7313819 dblp:conf/esscirc/Nikolic15 fatcat:tqsxgusdjzc5tbws2deheswziy

Warpbird: an Untethered System on Chip Using RISC-V Cores and the Rocket Chip Infrastructure

Luís Fiolhais, José T. de Sousa
2018 Zenodo  
This paper presents both a methodology for creating systems on chip (SoCs), using RISC-V cores, and a base open source SoC called Warpbird, which it is claimed here to be the first untethered SoC of its  ...  It is possible to license processor cores from providers such as ARM but this is still too expensive for many small enterprises.  ...  Chisel3 is built on top of Scala [19] , a Java-like language with support for functional programming and a static type system.  ... 
doi:10.5281/zenodo.3679370 fatcat:4goyxp43tvbmbmffwvkq7mrojm

A Hardware Co-design Workflow for Scientific Instruments at the Edge [article]

Kazutomo Yoshii, Rajesh Sankaran, Sebastian Strempfer, Maksim Levental, Mike Hammer, Antonino Miceli
2021 arXiv   pre-print
It can be a critical bottleneck for integration between scientific instruments at the edge and high-performance computers/emerging accelerators.  ...  This vision paper discusses hardware specialization needs in scientific instruments and briefly reviews our progress leveraging the Chisel hardware description language and emerging open-source hardware  ...  We also thank two anonymous referees for their useful comments. We thank Gail Pieper for editing this manuscript.  ... 
arXiv:2111.01380v1 fatcat:qau2ssyfvbgbdjo2gjcp7zpu5m

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

Süleyman Savas, Zain Ul-Abdin, Tomas Nordström
2018 Computers  
We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores.  ...  In this paper, we propose a design approach for high-performance, domain-specific heterogeneous architectures based on simple cores with application-specific extensions in the form of custom hardware blocks  ...  We would like to thank Struan Gray for his contributions with the language of the paper and to Schuyler Eldridge for his help with the accelerator integration.  ... 
doi:10.3390/computers7020027 fatcat:qktz2c36bbcxnj4bdrihwt35vq

Return of the Runtimes

Martin Maas, Krste Asanović, John Kubiatowicz
2017 Proceedings of the 16th Workshop on Hot Topics in Operating Systems - HotOS '17  
Managed languages such as Java, Python or Scala are widely used in this setting.  ...  We then outline the design of a general substrate for building such runtime systems, based on these seven tenets.  ...  Acknowledgements: Research was partially funded by DOE grant #DE-AC02-05CH11231, the STARnet Center for Future Architecture Research (C-FAR), and ASPIRE Lab sponsors and affiliates Intel, Google, HPE,  ... 
doi:10.1145/3102980.3103003 dblp:conf/hotos/MaasAK17 fatcat:qmj47ywapbgmnpm6aphkeq3wra

FPGA Acceleration for Big Data Analytics: Challenges and Opportunities

Joost Hoozemans, Johan Peltenburg, Fabian Nonnemacher, Akos Hadnagy, Zaid Al-Ars, H. Peter Hofstee
2021 IEEE Circuits and Systems Magazine  
However, networking and storage continue to provide both higher throughput and lower latency, which allows for leveraging heterogeneous components, deployed in data centers around the world.  ...  In this article, we focus on FPGA accelerators that have seen wide-scale deployment in large cloud infrastructures.  ...  The authors also thank Patrick Lysaght and Cathal McCabe from Xilinx for their support.  ... 
doi:10.1109/mcas.2021.3071608 fatcat:ywvymvx6bvc4dhytbgjcoqov2u

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

Mostafa W. Numan, Braden J. Phillips, Gavin S. Puddy, Katrina Falkner
2020 IEEE Access  
This paper is motivated by the idea of a software tool that can automatically accomplish the task of deploying code, originally written for a conventional computer, to the processors and reconfigurable  ...  computing systems with tightly coupled processors and reconfigurable logic blocks provide great scope to improve software performance by executing each section of code on the processor or custom hardware accelerator  ...  It allows developers to write SoC applications in C for the software part and in Behavioural Description Language (BDL) [65] for hardware accelerators.  ... 
doi:10.1109/access.2020.3024098 fatcat:hk7s2deq6zgp5fnuwvm5k6jodu

Spark Acceleration On Fpgas: A Use Case On Machine Learning In Pynq

Elias Koromilas, Ioannis Stamelos, Christoforos Kachris, Soudris. Dimitrios
2017 Zenodo  
In this paper, we present Spynq: A framework for the efficient deployment of data analytics on embedded systems that are based on the heterogeneous MPSoC FPGA called Pynq.  ...  Spark is one of the most widely used frameworks for data analytics. Spark allows fast development for several applications like machine learning, graph computations, etc.  ...  The FPGA boards can be hosted in typical servers and are utilized based on application specific libraries and framework integration for the five key workloads.  ... 
doi:10.5281/zenodo.801507 fatcat:d4cav7b3dre3vkrpvhieqde2au

Parallel Programming Models for Heterogeneous Many-Cores : A Survey [article]

Jianbin Fang, Chun Huang, Tao Tang, Zheng Wang
2020 arXiv   pre-print
In this article, we provide a comprehensive survey for parallel programming models for heterogeneous many-core architectures and review the compiling techniques of improving programmability and portability  ...  We examine various software optimization techniques for minimizing the communicating overhead between heterogeneous computing devices.  ...  To sum up, the domain-specific programming models have the potential to improve programmer productivity, to support domain-specific forms of modularity, and to use domain-specific information to support  ... 
arXiv:2005.04094v1 fatcat:e2psrdnyajh3hih3znnjjbezae

Spynq: Acceleration Of Machine Learning Applications Over Spark On Pynq

Christoforos Kachris, Elias Koromilas, Ioannis Stamelos, Dimitrios Soudris
2017 Zenodo  
In this paper, we present SPynq: A framework for the efficient utilization of hardware accelerators over the Spark framework on heterogeneous MPSoC FPGAs, such as Zynq.  ...  The performance evaluation shows that the heterogeneous accelerator-based MpSoC can achieve up to 2.3x system speedup compared with a Xeon system (with 90% accuracy) and 20x better energy efficiency.  ...  One option was to create a new serializer for the specific type of returned object and add this to Spark, but doing so would end up in a very complex implementation.  ... 
doi:10.5281/zenodo.836712 fatcat:dynuug3zanfypgywhb5qmofpnq

Parallel programming models for heterogeneous many-cores: a comprehensive survey

Jianbin Fang, Chun Huang, Tao Tang, Zheng Wang
2020 CCF Transactions on High Performance Computing  
In this article, we provide a comprehensive survey for parallel programming models for heterogeneous many-core architectures and review the compiling techniques of improving programmability and portability  ...  We examine various software optimization techniques for minimizing the communicating overhead between heterogeneous computing devices.  ...  To sum up, the domain-specific programming models have the potential to improve programmer productivity, to support domain-specific forms of modularity, and to use domain-specific information to support  ... 
doi:10.1007/s42514-020-00039-4 fatcat:nn56xhjm6rcu7kya6gfnyjg66q

PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research

Derek Lockhart, Gary Zibrat, Christopher Batten
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
PyMTL leverages the Python programming language to create a highly productive domainspecific embedded language for concurrent-structural modeling and hardware design.  ...  SimJIT+PyPy provides speedups of up to 72× for CL models and 200× for RTL models, bringing us within 4-6× of optimized C++ code while providing significant benefits in terms of productivity and usability  ...  for their help developing the C++ and Verilog mesh network models.  ... 
doi:10.1109/micro.2014.50 dblp:conf/micro/LockhartZB14 fatcat:45vwsdljefg35akasoy5ijyspu

IntelliSoC: A System Level Design and Conception of a System- on-a-Chip (SoC) to Cognitive Agents Architecture [chapter]

Diego Ferreira, Augusto Loureiro da Costa, Wagner Luiz Alves De Oliveira
2019 Applications of Mobile Robots  
This chapter presents a system level design and conception of a System-on-a-Chip (SoC) for the execution of cognitive agents.  ...  Thus, this work proposes a novel SoC whose architecture fits the computational demands of the aforementioned cognitive model, allowing for fast, energy-efficient, embedded intelligent applications.  ...  Case study The architecture were simulated using a program written in the Scala programming language, using array structures for the instruction, alpha and beta memories, lists for fork and JN test stacks  ... 
doi:10.5772/intechopen.79265 fatcat:uucfl4pz4fbvxbmhbyevg7hlaq
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