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Satisfiability-Based Functional Delay Fault Testing
[chapter]
2000
IFIP Advances in Information and Communication Technology
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In this paper we show that SAT-based functional delay fault testing can yield very competitive results with careful construction ofthe CNF formulas for the target faults. ...
Functional delay fault testing can also be used to derive test sets for IP (lntellectual Property) circuits whose implementation details are not provided. ...
In this paper, we present a SA T -based test pattern generation method for the functional delay fault model. ...
doi:10.1007/978-0-387-35498-9_32
fatcat:wb6ehq5xhbhslnpsuz4lcyyiom
On applying incremental satisfiability to delay fault testing
2000
Proceedings of the conference on Design, automation and test in Europe - DATE '00
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Application of ISAT to delay fault testing is presented by formulating incremental path sensitization as an ISAT problem. ...
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. ...
A test is called non-robust if the given fault can be masked by the presence of other delay faults in the circuit. Our experimental results are based on the non-robust delay fault testing model. ...
doi:10.1145/343647.343801
fatcat:gozzlhnokbf5blgmi7ehnmr6du
A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits
2011
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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fault function hazards, 28, 31, 42 function robust path delay faults, 28 functional block design, 18 functional redundant test, 18 functional testing, 6 functionally sensitizable test, 17, 18 functionally ...
A NEW MODEL FOR DELAY FAULT TESTING IN MACRO BASED ICS by a robust test independently of any other delay inside the circuit. ...
In order to satisfy the test quality requirements of nanoscale CMOS circuits, it should be noted that the extension of switch and gate level fault models to logic bricks may be not immediate because the ...
doi:10.1109/tcad.2010.2093290
fatcat:7fjxwqwf4fddxnzbq357clqsty
Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization
2014
2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
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It is well-known that in principle automatic test pattern generation (ATPG) can be solved by transforming the circuit and the fault considered into a Boolean satisfiability (SAT) instance and then calling ...
a so-called SAT solver to compute a test. ...
the above to a microprocessor environment and automatically generate functional mi-croprocessor test sequences, e.g., for small-delay faults, based on Bounded Model Checking. ...
doi:10.1109/dtis.2014.6850674
dblp:conf/dtis/BeckerDES14
fatcat:xwlu3jwerjhjtdkq26cjdildpu
RTL Test Point Insertion to Reduce Delay Test Volume
2007
Proceedings of the ... IEEE VLSI Test Symposium
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Test points are identified based on functional information of RTL primitives using a satisfiability based algorithm. ...
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. ...
Scan-based delay testing (esp. transition fault testing) has become an integral part of the structural Design-for-Test (DFT) flow. ...
doi:10.1109/vts.2007.55
dblp:conf/vts/BalakrishnanF07
fatcat:fajjycheqbf3flou7cdrofkwgq
Automatic test pattern generation for delay defects using timed characteristic functions
2013
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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This paper proposes a viable ATPG method based on a satisfiability (SAT) formulation using timed characteristic functions (TCFs), which gained notable scalability enhancement very recently. ...
Experimental results show promising runtime and fault coverage improvements over prior SAT-based timing-aware ATPG methods. ...
FROM FUNCTIONAL TIMING ANALY-SIS TO DELAY TESTING In TCF-based functional timing analysis [14] , a circuit is assumed to operate under the floating mode. ...
doi:10.1109/iccad.2013.6691103
dblp:conf/iccad/HoLYKLJL13
fatcat:pjn2bzpd75gz5ncxamuqr2yzlq
An efficient delay test generation system for combinational logic circuits
1990
Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90
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be tested with any static test generation methods based upon the steady-state response analysis. ...
is an objective to be satisfied for fault excitation. ...
ACKNOWLEDGEMENT The implementation of the DTEST-GEN system is based upon the UT-PODEM and FAN which were developed by authors, Hyoung B. Min. and Dr. William A. Rogers. ...
doi:10.1145/123186.123390
dblp:conf/dac/ParkM90
fatcat:swhac2nlpbflnpwfm2hna7mzei
An efficient delay test generation system for combinational logic circuits
1992
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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be tested with any static test generation methods based upon the steady-state response analysis. ...
is an objective to be satisfied for fault excitation. ...
ACKNOWLEDGEMENT The implementation of the DTEST-GEN system is based upon the UT-PODEM and FAN which were developed by authors, Hyoung B. Min. and Dr. William A. Rogers. ...
doi:10.1109/43.144857
fatcat:uf5sntpsxfhe5nntug23vcvcpa
Fast identification of untestable delay faults using implications
1997
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97
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Targeting untestable delay faults for test generation by an automatic test pattern generation (ATPG) tool can be avoided. ...
The method works for the segment delay fault model and its special case, the path delay fault model, and identifies robustly untestable, non-robustly untestable, and functionally unsensitizable delay faults ...
Functional Unsensitizability Analysis Functionally unsensitizable path faults can be ignored during delay fault testing and timing analysis [11] . ...
doi:10.1109/iccad.1997.643606
dblp:conf/iccad/HeraguPA97
fatcat:uwe32a3mhjbrfi4vx5oew3izhe
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
2012
2012 IEEE 21st Asian Test Symposium
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As a result, the faults are detected through the longest robustly testable path, i.e. independently from other delay faults. ...
Advances in the chip manufacturing process impose new requirements for post-production test. Small Delay Defects (SDDs) have become a serious problem during chip testing. ...
Here, As-Robust-As-Possible tests are generated for the path delay fault model. An optimization function is used to satisfy as much robust sensitization conditions as possible for a specified path. ...
doi:10.1109/ats.2012.35
dblp:conf/ats/EggersglussYC12
fatcat:bmc4zlbvkbaijn7soqkpsvkomq
An effective approach to automatic functional processor test generation for small-delay faults
2014
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014
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In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. ...
In our experiments we were able to reach over 97 % fault efficiency. To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults. ...
The aim of this work is the automatic generation of functional tests targeting small-delay faults in microprocessors. ...
doi:10.7873/date.2014.140
dblp:conf/date/RiefertCSBRB14
fatcat:due7r2cknfejlnorcvbnyqag54
Generating Boolean SAT based Test Pattern Generation using Multi-objective Genetic Algorithm
2010
International Journal of Computer Applications
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In this paper we have discussed that how test pattern generation method can be formulated in terms of CNF form [2]and this CNF form can be used to generate test patterns using genetic algorithm. ...
We have proposed that by applying a multi-objective genetic algorithm on this CNF form we can increase number of instances to satisfy boolean equation. ...
In the second phase the GA phase the test vectors are evolved based on fitness function [14] .The fitness function used is : drop the faults detected by that sequence; } } return (initial population); ...
doi:10.5120/1099-1438
fatcat:cfhmtxalqramrjmkshtct53huy
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths
2005
14th Asian Test Symposium (ATS'05)
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Target circuit and fault An RTL design generally consists of controller and data path, and they are connected each other by control signal ...
two-pattern tests. ...
The remaining testable path delay faults are FS path delay faults. To test these faults, transitions are needed at multiple inputs. ...
doi:10.1109/ats.2005.47
dblp:conf/ats/YoshikawOIF05
fatcat:zghjjokvojciznyjusdvwrvf3q
High-Level Test Synthesis for Delay Fault Testability
2007
2007 Design, Automation & Test in Europe Conference & Exhibition
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Experimental results show that this method achieves 100% fault coverage for transition faults in functional units, while the fault coverage in circuits synthesized by LEA-based allocation algorithm is ...
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. ...
However, there are many complicating factors when moving from relatively slow scan-based tests for stuck-at faults to testing for delay faults. ...
doi:10.1109/date.2007.364565
dblp:conf/date/WangY07
fatcat:5lolwle4rvbhdcjp5ctijzudvi
Design and Implementation of Low Power Testing Using Advanced Razor Based Processor
2017
Zenodo
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A low-power broadside test set is shown from a functional broadside set with the derivation of skewed load test cubes in BIST circuits The twin effect of programmable truncated multiplication and fault-tolerant ...
In order to cope up with the functional operation criteria, our work concentrate on the percentage of indefinite values in the tests performed. ...
When the functional test sequences satisfy functional constraints on primary input sequences, the functional broadside tests that are extracted from them satisfy the same constraints. ...
doi:10.5281/zenodo.3608360
fatcat:cq4ffqpfwzbm3g5eq3eq2qgbbm
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