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DracoSTM

Justin E. Gottschlich, Daniel A. Connors
2007 Proceedings of the 2007 Symposium on Library-Centric Software Design - LCSD '07  
DracoSTM is the STM first solution to (1) implement both direct and deferred updating and (2) enable run-time alternation between these updating policies.  ...  Transactional memory (TM) is a recent parallel programming concept which reduces challenges found in parallel programming.  ...  We also give our thanks to Lori Peek-Gottschlich, Sue Lewis and Dwight Winkler for their numerous edits and valuable feedback.  ... 
doi:10.1145/1512762.1512768 fatcat:a4urjmloircdbd4dgxt4qav7he

Safety of Deferred Update in Transactional Memory [article]

Hagit Attiya, Sandeep Hans, Petr Kuznetsov, Srivatsan Ravi
2013 arXiv   pre-print
\emph{deferred-update} semantics.  ...  We show that our criterion is a safety property, i.e., it is prefix- and limit-closed.  ...  Acknowledgements: The last author would like to thank Victor Luchangco for interesting discussions on opacity during PODC'12 and anonymous reviewers of WTTM'12 for comments on a nascent version of this  ... 
arXiv:1301.6297v3 fatcat:oqsylfc4tjeedjzsx4nzmn46vi

Software Transactional Memory on Relaxed Memory Models [chapter]

Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
2009 Lecture Notes in Computer Science  
These assumptions are often violated in realistic settings, as STM implementations run on relaxed memory models, with the atomicity of operations as provided by the hardware.  ...  We use FOIL to verify DSTM, TL2, and McRT STM under the memory models of sequential consistency, total store order, partial store order, and relaxed memory order.  ...  Transactional locking II (TL2) is an STM algorithm, which is highly popular for its good performance. It is a deferred-update STM, and uses locks to ensure safety.  ... 
doi:10.1007/978-3-642-02658-4_26 fatcat:s5qqk7rpjbbxzdiflnbwzyi6lu

Safety of Deferred Update in Transactional Memory

Hagit Attiya, Sandeep Hans, Petr Kuznetsov, Srivatsan Ravi
2013 2013 IEEE 33rd International Conference on Distributed Computing Systems  
deferred-update semantics.  ...  We show that our criterion is a safety property, i.e., it is prefix-and limit-closed.  ...  This is usually referred to as the deferred-update semantics, and it was in fact used in some representations of opacity [3] . The motivation of this paper is to capture this intuition formally.  ... 
doi:10.1109/icdcs.2013.57 dblp:conf/icdcs/AttiyaHKR13 fatcat:u3etwqzpynb7djgnn6ebe6nglm

Data validation for business continuity planning

Soujanya Soni, Sameep Mehta, Sandeep Hans
2012 Proceedings of 2012 IEEE International Conference on Service Operations and Logistics, and Informatics  
My role included doing enhancements to the existing code base and fixing issues related to Client Side components.  ...  Complete Product ownership of Symantec LiveState Delivery-an enterprise level client management suite involving development, maintenance and releases.  ...  Safety of Deferred Update in Transactional Memory. In ICDCS, 2013. Hagit Attiya and Sandeep Hans. Transactions are Back-but How Different They Are? In TRANSACT, 2012.  ... 
doi:10.1109/soli.2012.6273507 dblp:conf/soli/SoniMH12 fatcat:763acem42jhn3cnixxbslcfnce

Concurrency control with data coloring

Luis Ceze, Christoph von Praun, Călin Caşcaval, Pablo Montesinos, Josep Torrellas
2008 Proceedings of the 2008 ACM SIGPLAN workshop on Memory systems performance and correctness held in conjunction with the Thirteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '08) - MSPC '08  
Concurrency control is one of the main sources of error and complexity in shared memory parallel programming.  ...  While there are several techniques to handle concurrency control such as locks and transactional memory, simplifying concurrency control has proved elusive.  ...  Omitting color steps affects liveness properties but not safety. Transaction Inference Domain-level consistency can be implemented using transactional memory (TM).  ... 
doi:10.1145/1353522.1353525 dblp:conf/asplos/CezePCMT08 fatcat:a32yguryz5evtc72fxyq3hk53a

Reducing Memory Ordering Overheads in Software Transactional Memory

Michael F. Spear, Maged M. Michael, Michael L. Scott, Peng Wu
2009 2009 International Symposium on Code Generation and Optimization  
Using these techniques, we obtain a reduction of up to 89% in the number of fences, and 20% in per-transaction latency, for common transactional benchmarks.  ...  Most research into high-performance software transactional memory (STM) assumes that transactions will run on a processor with a relatively strict memory model, such as Total Store Ordering (TSO).  ...  We also thank Kyle Liddell and James Roche for their support.  ... 
doi:10.1109/cgo.2009.30 dblp:conf/cgo/SpearMSW09 fatcat:azca7777dzfw3mwuh7ykhywwlu

Verification of STM on relaxed memory models

Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
2011 Formal methods in system design  
Software transactional memories (STM) are described in the literature with assumptions of sequentially consistent program execution and atomicity of high level operations like read, write, and abort.  ...  However, in a realistic setting, processors use relaxed memory models to optimize hardware performance. Moreover, the atomicity of operations depends on the underlying hardware.  ...  Opacity We consider opacity [22] as the correctness (safety) requirement of transactional memories.  ... 
doi:10.1007/s10703-011-0131-3 fatcat:ltqb5euegzhgjofh46kloh5jsu

Persistent messages in local transactions

David E. Lowell, Peter M. Chen
1998 Proceedings of the seventeenth annual ACM symposium on Principles of distributed computing - PODC '98  
Under this model, messages and data are not lost after crashes, and all sends and receives are performed in local transactions.  ...  We present a new model for handling messages and state in a distributed application that we call Messages in Local Transactions (MLT).  ...  The transaction mechanism guarantees that either all the updates in a transaction will take place, or none will, and maintains this invariant even if a crash occurs in the middle of processing the transaction  ... 
doi:10.1145/277697.277737 dblp:conf/podc/LowellC98 fatcat:zgdnwtgc4vc4tjfvjr3rdaysfi

WTTM 2012, the fourth workshop on the theory of transactional memory

Vincent Gramoli, Alessia Milani
2012 ACM SIGACT News  
In conjunction with PODC 2012, the TransForm project (Marie Curie Initial Training Network) and EuroTM (COST Action IC1001) supported the 4th edition of the Workshop on the Theory of Transactional Memory  ...  The objective of WTTM was to discuss new theoretical challenges and recent achievements in the area of transactional computing. The workshop took place on July 19, 2012, in Madeira, Portugal.  ...  Acknowledgements We are grateful to the speakers, to the program committee members of WTTM 2012 for their help in reviewing this year's submissions and to Panagiota Fatourou for her help in the organization  ... 
doi:10.1145/2421119.2421141 fatcat:ki2pxs4enrggfkpsj2jys76prm

Operating systems transactions

Donald E. Porter, Owen S. Hofmann, Christopher J. Rossbach, Alexander Benn, Emmett Witchel
2009 Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles - SOSP '09  
System transactions allow the programmer to specify updates to heterogeneous system resources with the OS guaranteeing atomicity, consistency, isolation, and durability (ACID).  ...  Applications must be able to synchronize accesses to operating system resources in order to ensure correctness in the face of concurrency and system failures.  ...  TxOS's memory use indicates that buffering transactional updates in memory is practical, especially considering the trend in newer systems toward larger DRAM and 64-bit addresses.  ... 
doi:10.1145/1629575.1629591 dblp:conf/sosp/PorterHRBW09 fatcat:vwkhrgvvuna5tbx2mowbmo3dde

Hardware tansactional memory support for lightweight dynamic language evolution

Nicholas Riley, Craig Zilles
2006 Companion to the 21st ACM SIGPLAN conference on Object-oriented programming systems, languages, and applications - OOPSLA '06  
We eliminate common transactional conflicts and defer I/O within transactions to make parallel Python execution both possible and efficient.  ...  We propose the use of hardware transactional memory (HTM) to aid runtimes in evolving more capable and robust execution models while maintaining native code compatibility.  ...  Acknowledgments This research was supported in part by NSF CCR-0311340, NSF CAREER award CCR-03047260, and a gift from the Intel corporation.  ... 
doi:10.1145/1176617.1176758 dblp:conf/oopsla/RileyZ06 fatcat:ghn7hmicevdh7plv7yosemiddi

Towards Automatic Lock Removal for Scalable Synchronization [chapter]

Maya Arbel, Guy Golan-Gueta, Eshcar Hillel, Idit Keidar
2015 Lecture Notes in Computer Science  
The main idea is to have each operation perform an optimistic traversal of the data structure as long as no shared memory locations are updated, and then proceed with pessimistic code.  ...  Our transformation takes lock-based code and replaces some of the locking steps therein with optimistic synchronization in order to reduce contention.  ...  overhead associated with speculative or deferred shared memory updates, (as occurs in software transactional memory (STM) [30] ).  ... 
doi:10.1007/978-3-662-48653-5_12 fatcat:4zstkfjfe5hthd4atewlaekn74

Transactional Encoding for Tolerating Transient Hardware Errors [chapter]

Jons-Tobias Wamhoff, Mario Schwalbe, Rasha Faqeh, Christof Fetzer, Pascal Felber
2013 Lecture Notes in Computer Science  
Transactional encoding relies on a combination of arithmetic codes for detecting transient hardware errors and transactional memory for recovery and tolerance of transient errors.  ...  In this paper, we propose and evaluate transactional encoding, a novel approach to detect and mask transient hardware errors such that one can build safe applications on top of unreliable components.  ...  This work is partly supported by the German Research Foundation (DFG) within the Cluster of Excellence Center for Advancing Electronics Dresden and by the European Communitys Seventh Framework Programme  ... 
doi:10.1007/978-3-319-03089-0_1 fatcat:uf7jwsi2azeevfajypjbnoeace

A Replication Protocol Supporting Multiple Consistency Models without Single Point of Failure

Atsushi OHTA, Ryota KAWASHIMA, Hiroshi MATSUO
2016 IEICE transactions on information and systems  
In this paper, we introduce the multi-consistency support mechanism of McRep to a combined statemachine and deferred-update replication protocol to eliminate the performance bottleneck and SPoF.  ...  Each replica has new roles in serialization of all transactions and managing all views of the database, and each client has a new role in managing status of its transactions.  ...  Acknowledgments This work was supported in part by MEXT KAKENHI Grant Number 24500113 and 15K00168.  ... 
doi:10.1587/transinf.2016pap0014 fatcat:luiirpgjpvajlc5oumhgt2bsei
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