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This paper applies the STEPS methodology to SoCs containing a VCIcompliant interconnect, a microprocessor, P1500 compliant IP cores and an external RAM controller interface. ... This paper presents STEPS, an innovative softwarebased approach for testing P1500-compliant SoCs. ... For that purpose, we have developed a new SoC test methodology called STEPS (Software-based Test Environment for P1500 compliant SoCs), that replaces the ATE by a simple RAM of huge capacity containing ...doi:10.1109/date.2004.1268943 dblp:conf/date/BenabdenbiGPVT04 fatcat:4b7dg3aggzfnlc2qaxzkojbary
Proceedings. 42nd Design Automation Conference, 2005.
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. ... By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock ... This solution described a P1500-compliant wrapper  , which effectively solved the clock skew problem. ...doi:10.1109/dac.2005.193785 fatcat:ckx7tyhk5jerhdjo2ri2zcwthm
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. ... By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock ... This solution described a P1500-compliant wrapper  , which effectively solved the clock skew problem. ...doi:10.1145/1065579.1065615 dblp:conf/dac/XuNC05 fatcat:ffoaey6uojgwhmrv2epykhcqpu
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-achip (SoC) environments. ... The approach advantages are the ability to protect the core IP, the simple test interface (thanks also to the adoption of the P1500 standard), the possibility to run the test at-speed, the reduced test ... In this paper we report the experience gathered by adopting a test strategy for logic cores based on a custom BIST engine wrapped to the embedded device under test. ...doi:10.1109/date.2005.305 dblp:conf/date/BernardiMQR04 fatcat:d246tesdonbvhbkgqfqnuuluse
To understand the unique challenges in IP development and SoC integration, a microprocessor core and a network processor SoC were developed. ... System-on-a-chip (SoC) and reuse of intellectual property (IP) is the emerging paradigm for integrated circuit designs. ... I 220.127.116.11 18.104.22.168 | 22.214.171.124 Routi I 126.96.36.199 | I 188.8.131.52 | 184.108.40.206 | 168.1.4.x Table 2 . 2 Core DFT strategy For testing at the system level, P1500-compliant wrappers were ...doi:10.14288/1.0065553 fatcat:elkp6f6w5bei3myp4qfy4t4c3e
For this purpose, the IEEE P1500 standard for embedded-core test is under development. The P1500 standard strives to provide a "plugand-play" methodology of integrating core testability into a SoC. ... Introduction As mentioned in chapter 1 the new SoC design philosophy based on a hierarchical reuse of already made cores, requires the adoption of IP test infrastructures able to fully support core reuse ... possible ATSP solution is the following GTS: The process of March Test generation from a GTS passes through three different steps: • GTS reordering • GTS minimization • March Test Generation Each step ...doi:10.6092/polito/porto/2709266 fatcat:zulzplxkhnbyjdpentdj77z2hy