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Analysis of Current Mirrors with Asymmetric Self-Cascode Association of SOI MOSFETs through SPICE Simulations

Paulo Rodrigues da Silva, Michelly De Souza
2020 Journal of Integrated Circuits and Systems  
A comparison of current mirrors figures of merit, looking for the advantages of the asymmetric composite structure in relation to a single SOI MOSFETs and the symmetric self-cascode transistor is performed  ...  In this paper the performance of different architectures of current mirrors implemented with single SOI transistors and self-cascode transistors, both symmetric and asymmetric is evaluated.  ...  with Asymmetric Self-Cascode Association of SOI MOSFETs through SPICE Simulations Fig. 1 Schematic representation of a self-cascode transistor.  ... 
doi:10.29292/jics.v15i2.159 fatcat:5fjhddd3avdwnfo2dy55u3itv4

SOI/SOS MOSFET universal compact SPICE model with account for radiation effects

Konstantin O. Petrosyants, Igor A. Kharitonov, Lev M. Sambursky
2015 EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon  
Examples of radhard SOI/SOS CMOS circuits simulation are presented.  ...  Universal SPICE model for submicron SOI/SOS MOSFETs based on BSIMSOI and EKV-SOI platforms with account for total ionizing dose-induced effects (TID), pulsed radiation effects, single events is presented  ...  EXAMPLES OF CIRCUIT DESIGN The model was implemented in circuit simulators HSpice, Spectre, Eldo and others and extensively applied to simulation of radiation-hard digital, analog, and mixed-signal integrated  ... 
doi:10.1109/ulis.2015.7063834 fatcat:2l7amlqsm5fttg2bubwusqzqqi

Analytical Modeling of Realistic Single-Electron Transistors Based on Metal-Oxide-Semiconductor Structure with a Unique Distribution Function in the Coulomb-Blockade Oscillation Region

Kyung Rok Kim, Ki-Whan Song, Dae Hwan Kim, Gwanghyeon Baek, Hyun Ho Kim, Jung Im Huh, Jong Duk Lee, Byung-Gook Park
2004 Japanese Journal of Applied Physics  
In order to validate the operation principle of our device, we have implemented an analytical device model in the simulation program with integrated circuit emphasis (SPICE).  ...  SPICE simulation of our model with a unique distribution function has reproduced the experimental results with good agreement for wide gate and drain bias range.  ...  Acknowledgements This research was supported by the BK21 Program and ''Development of Nanoelectronic Devices and Circuit Technology'' from Korean Ministry of Commerce, Industry, and Energy.  ... 
doi:10.1143/jjap.43.2031 fatcat:2dj3xhwuufhhhgjuio4g2tbcpe

Author Index

2020 2020 IEEE Latin America Electron Devices Conference (LAEDC)  
Method Based On A Trapezoidal Shape For Edgeless Gate Enclosed (EGE) MOSFET Width Over Length Calculation SPICE Simulation of Radiation Induced Charges and Currents in Silicon Substrate Assessing  ...  RRAM Dukanov, Pavel Microwave High-Voltage CBiCJFET Technology for Analog Integrated Circuits Dumollard, Yannick Equation-based modeling of electrothermal behavior of a SiC MOSFET chip during a  ... 
doi:10.1109/laedc49063.2020.9073278 fatcat:jsl333rxxjfi7nkkiojoao7in4

Development FD-SOI MOSFET amplifiers for integrated read-out circuit of superconducting-tunnel-junction single-photon-detectors [article]

Kenji Kiuchi, Shinhong Kim, Yuji Takeuchi, Kenichi Takemasa, Kazuki Nagata, Kota Kasahara, Koya Moriuchi, Ren Senzaki, Shunsuke Yagi, Hirokazu Ikeda, Shuji Matsuura, Takehiko Wada (+17 others)
2015 arXiv   pre-print
We proposed an FD-SOI MOSFET based charge integrated amplifier design as a read-out circuit of STJ detectors.  ...  Taking into account these effects, FD-SOI MOSFETs are available for read-out circuit of STJ detectors.  ...  ACKNOWLEDGEMENTS This work was supported by the Ministry of Education, Science, Sports and Culture of Japan (MEXT KAKENHI Grant Number 25105007).  ... 
arXiv:1507.07424v1 fatcat:pzexdvsia5bcdkvdzjxpo4ambm

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring

Maria Malits, Igor Brouk, Yael Nemirovsky
2018 Sensors  
This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology.  ...  The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K-500 K temperature range while consuming only 30 µW  ...  The help of Ida Shumpei from Murata in the transient simulations is highly appreciated. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/s18051629 pmid:29783742 pmcid:PMC5982330 fatcat:f53ok6cq3jhbpkccsisg5nrrha

SOI transistor model for fast transient simulation

D. Nadezhin, S. Gavrilov, A. Glebov, Y. Egorov, V. Zolotov, D. Blaauw, R. Panda, M. Becer, A. Ardelea, A. Patel
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
We propose using body charge instead of body potential as an independent variable of the model to improve convergence of circuit simulation integration algorithm.  ...  However, design and simulation of SOI MOS circuits is more challenging due to more complex behavior of an SOI transistor involving floating body effects, delay dependence on history of transistor switching  ...  Fast transient simulators for SOI circuits are even more beneficial than for bulk CMOS circuits as the speed of SPICE simulators for SOI circuits is usually much less than for bulk ones.  ... 
doi:10.1109/iccad.2003.159680 fatcat:evacyrn76je5lplyq456dxfeoe

Analysis of Mobility in Graded-Channel SOI Transistors Aiming at Circuit Simulation

Lucas Mota Barbosa da Silva, Bruna Cardoso Paz, Michelly De Souza
2020 Journal of Integrated Circuits and Systems  
The parameters extracted from experimental data were used in a SPICE simulator, showing that it is possible to simulated GC SOI MOSFET using a regular SOI MOSFET model, by adjusting its parameters.  ...  This work presents an analysis of the behavior of the effective mobility of graded-channel FD SOI transistors using an Y-Function-based technique.  ...  Analysis of Mobility in Graded-Channel SOI Transistors Aiming at Circuit Simulation Table 1 - 1 Dimensions of simulated GC SOI transistors and extracted threshold voltage.  ... 
doi:10.29292/jics.v15i2.188 fatcat:62svhsqpffafrbjrqwepq7mmau

Compact Modeling of 0.35 micron SOI CMOS Technology Node for 4 K DC Operation using Verilog-A [article]

A. Akturk, K. Eng, J. Hamlet, S. Potbhare, E. Longoria, R. Young, M. Peckerar, T. Gurrieri, M. S. Carroll, N. Goldsman
2010 arXiv   pre-print
The 4 K DC behavior is reproduced well by the compact model and the model seamlessly evolves during simulation of circuits and systems as the simulator encounters SOI MOSFETs with different lengths and  ...  Compact modeling of MOSFETs from a 0.35 micron SOI technology node operating at 4 K is presented.  ...  The model seamlessly evolves during simulation of circuits and systems as the simulator encounters SOI MOSFETs with different lengths and widths.  ... 
arXiv:1001.3353v1 fatcat:r5qgnnrzhjflhb4bqc3to2lvmm

SOI thermal impedance extraction methodology and its significance for circuit simulation

Wei Jin, Weidong Liu, S.K.H. Fung, P.C.H. Chan, Chenming Hu
2001 IEEE Transactions on Electron Devices  
After SHE is accounted for, the frequency-dependent SHE may be disabled in circuit simulation without sacrificing the accuracy, thus providing faster circuit simulation for high-frequency circuits.  ...  Index Terms-Self-heating effect (SHE), SOI MOSFET, thermal impedance.  ...  Hu and his group as a major developer of the BSIM3v3 and BSIM4 MOSFET models for circuit simulation, and providing technical support of the BSIM models for industry and research community worldwide.  ... 
doi:10.1109/16.915707 fatcat:bkf7wyn6tng2bgee3xhpdimu7m

Keyword Index

2021 2021 IEEE Latin America Electron Devices Conference (LAEDC)  
Bsim soi Strategy for Simulation of Analog Circuits with GCSOI MOSFET using BSIM SOI model Bti Circuit reliability prediction: challenges and solutions for the device time-dependent variability characterization  ...  (SOI) SOI technologies for RF and millimeter-wave integrated circuits SOI technologies for RF and millimeter-wave integrated circuits RF measurements technology Influence of Calibration Methods and RF  ...  Substrate effect Assessment of RF compact modelling of FD SOI transistors Surface recombination velocity  ... 
doi:10.1109/laedc51812.2021.9437930 fatcat:3tanameu3fa6jiubgbtih53z4y

A dc model for partially depleted SOI laterally diffused MOSFETs utilizing the HiSIM-HV compact model

Tarun Kumar Agarwal, M. Jagadesh Kumar
2013 Journal of Computational Electronics  
The model is validated for a set of channel and drift lengths to demonstrate the scalability of the model. The accuracy of the proposed subcircuit model is verified using 2-D numerical simulations.  ...  The high-voltage effects, due to the surface MOS region of PD SOI LDMOSFET, are modeled using the HiSIM-HV model.  ...  Therefore, the developed compact models here will enable the accurate design of complex circuits, using PD SOI LD-MOS devices based on SPICE simulation.  ... 
doi:10.1007/s10825-013-0457-8 fatcat:ykdiitoayrep7lcqcsra4iiuuu

Nonresonant detection of terahertz radiation by silicon-on-insulator MOSFETs

N. Pala, F. Teppe, D. Veksler, Y. Deng, M.S. Shur, R. Gaska
2005 Electronics Letters  
The observed effect could be used for nondestructive, contactless testing of silicon very large integrated circuits in situ.  ...  In this Letter, we present experimental evidence of the THz detection by silicon-on-insulator (SOI) MOSFETs in the temperature range from 8 to 350 K under different drain bias conditions.  ...  Polonsky of IBM for samples and A. Dmitriev and V. Kachorovski for valuable discussions.  ... 
doi:10.1049/el:20058182 fatcat:53ycg75ctvcbhczed2ado6jlu4

Compact modeling for the changing transistor

Chenming Hu
2013 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)  
Compact model can address not only circuit performance but also reliability. BSIM and BERT are used as examples.  ...  It needs not only a mathematical model of a prototype transistor but also accurate models of many real device effects of the modern transistor.  ...  The compact model may be used with SPICE to simulate and design circuits directly.  ... 
doi:10.1109/sispad.2013.6650571 fatcat:zj7ychg4ajhv5dpzkor5p7fgsy

Analytical modeling of field-induced interband tunneling-effect transistors and its application

Seung-Hwan Song, Kyung Rok Kim, Sangwoo Kang, Jin Ho Kim, Jung Im Huh, Kwon Chil Kang, Ki-Whan Song, Jong Duk Lee, Byung-Gook Park
2006 IEEE transactions on nanotechnology  
Due to the inherent SOI-MOSFET structure of the FITET, the current equation of MOSFET has also been included in the analytical equation of the FITET.  ...  SPICE simulation results with this analytical model have shown good agreements with the experimental results.  ...  Analytical model is applied to verify the functionality of these digital logic circuits in the simulation program with integrated circuit emphasis (SPICE). II.  ... 
doi:10.1109/tnano.2006.869950 fatcat:fy24wpe7yjfvrgosd74cs3lmye
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