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SPEED

Sumit Gulwani, Krishna K. Mehra, Trishul Chilimbi
2008 Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '09  
Such computational complexity bounds for even simple programs are usually disjunctive, non-linear, and involve numerical properties of heaps.  ...  Our algorithm generates complexity bounds that are usually precise not only in terms of the computational complexity, but also in terms of the constant factors.  ...  We thank Lakshmisubrahmanyam Velaga for implementing the abstract interpreter for uninterpreted functions, and a general combination framework for abstract interpreters, which was used as part of the SPEED  ... 
doi:10.1145/1480881.1480898 dblp:conf/popl/GulwaniMC09 fatcat:b2ub2i5ux5bjbic5jmju4x2is4

SPEED

Sumit Gulwani, Krishna K. Mehra, Trishul Chilimbi
2009 SIGPLAN notices  
Such computational complexity bounds for even simple programs are usually disjunctive, non-linear, and involve numerical properties of heaps.  ...  Our algorithm generates complexity bounds that are usually precise not only in terms of the computational complexity, but also in terms of the constant factors.  ...  We thank Lakshmisubrahmanyam Velaga for implementing the abstract interpreter for uninterpreted functions, and a general combination framework for abstract interpreters, which was used as part of the SPEED  ... 
doi:10.1145/1594834.1480898 fatcat:uashvxvlhfdofaczul2kvqubqm

High speed numerical integration algorithm using FPGA

F. N. A. Razak, M. S. A. Talip, M.F.M. Yakub, A.S.M. Khairudin, T.F.T.M.N. Izam, F. H. K. Zaman
2018 Journal of Fundamental and Applied Sciences  
Field Programmable Gate Arrays (FPGAs) can be used as a efficient and reliable alternative to implement the proposed a hardware implementation of four numerical integration algorithms using FPGA.  ...  The system performance is evaluated based on target chip Altera Cyclone IV FPGA in the metrics of resources utilization, clock latency, execution time, power consumption and computational error compared  ...  It is related to the used of parallel processing for any complex and intensive application program to run faster, efficient and reliable.  ... 
doi:10.4314/jfas.v9i4s.7 fatcat:spxnhbhl3vf7taupheq2puz3h4

Advisory speed for Intelligent Speed Adaptation in adverse conditions

Romain Gallen, Nicolas Hautiere, Sebastien Glaser
2010 2010 IEEE Intelligent Vehicles Symposium  
First, the 85 th percentile of observed speeds (V85) is estimated along a road, this speed profile is considered as a reference speed practised and practicable in ideal conditions for a lonely vehicle.  ...  It estimates an appropriate speed by fusing in real-time the outputs of ego sensors which detect adverse conditions with roadway characteristics transmitted by distant servers.  ...  We would like to thank CETE Normandie-Centre for providing us with speed profiles along the road and CETE Lyon for providing us with measured characteristics of the roads.  ... 
doi:10.1109/ivs.2010.5548035 dblp:conf/ivs/GallenHG10 fatcat:u44lcnpgmvbtrmv5kb3zxpbbqy

SPEED: Symbolic Complexity Bound Analysis [chapter]

Sumit Gulwani
2009 Lecture Notes in Computer Science  
The SPEED project addresses the problem of computing symbolic computational complexity bounds of procedures in terms of their inputs.  ...  We discuss some of the challenges that arise and present various orthogonal/complementary techniques recently developed in the SPEED project for addressing these challenges.  ...  We thank Varun Aggarwala and Aditya Nori for providing useful feedback on a draft of this paper.  ... 
doi:10.1007/978-3-642-02658-4_7 fatcat:h5hf2uaohzaf7oonfqlkcfjh7y

Speeding up Statistical Tolerance Analysis to Real Time

Peter Grohmann, Michael S. J. Walter
2021 Applied Sciences  
Furthermore, we identified a significant potential for reducing runtime by using array vectorization with NumPy, the proper selection of row- and column- major order, and the use of single precision floating-point  ...  computers.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/app11094207 doaj:717e23a58b4b495380e660f76b2033a5 fatcat:kpk62trc3ba2zessa5ypmu3aqy

Speeding Up Constraint Propagation [chapter]

Christian Schulte, Peter J. Stuckey
2004 Lecture Notes in Computer Science  
This paper presents a model and implementation techniques for speeding up constraint propagation.  ...  for greater efficiency.  ...  A rather obvious way to further speed up constraint propagation is to consider not only cost but also estimated impact for a propagator.  ... 
doi:10.1007/978-3-540-30201-8_45 fatcat:zzspbuu5fvdrfjaqj6k3vpjsfa

Hopf-Bifurcation Analysis of Airfoil Flutter at Transonic Speeds

Scott A. Morton, Philip S. Beran
1999 Journal of Aircraft  
The direct, Hopf-point method is found to be precise and efficient for grids typical of inviscid, transonic airfoil calculations.  ...  Flutter boundaries are also obtained through variation of static pretwist and pitch and plunge damping.  ...  Opportunities exist for more efficient computation of these matrices, through improved programming of the computational procedure for G, which the authors are currently exploring.  ... 
doi:10.2514/2.2447 fatcat:sijeafjy7rcudf74vlhabsc32e

A Novel High-Speed 54×54 bit Multiplier

Pouya Asadi, Keivan Navi
2007 American Journal of Applied Sciences  
This paper presents a self-timed carry-lookahead adder in which the logic complexity was a linear function of n, the number of inputs, and the average computation time was proportional to the logarithm  ...  The total number of transistors of the proposed multiplier core was 42579 and The multiplication time was 3.4 ns at a 1.3 V power supply.  ...  The tree-like circuit, shown inFig. 4, does not take full advantage of this feature to speed up the carry computation.  ... 
doi:10.3844/ajassp.2007.666.672 fatcat:jekkqpwxxfdabdqvx34gufi7ru

MDL convergence speed for Bernoulli sequences

Jan Poland, Marcus Hutter
2006 Statistics and computing  
We discuss the application to Machine Learning tasks such as classification and hypothesis testing, and generalization to countable classes of i.i.d. models.  ...  (b) it additionally specifies the convergence speed.  ...  (As already mentioned, the terms predictor and estimator coincide for static MDL and Bernoulli classes.)  ... 
doi:10.1007/s11222-006-6746-3 fatcat:va7meu52nzdwvi6ktcdbdl3byq

Object Recognition Speed Improvement Using Bitmap-Hog

Alireza Dehghani, David Moloney, Ivan Griffin
2016 Zenodo  
about 5% in recall and a decrease about 2% in precision in comparison with standard HoG.  ...  Commonly, HoG/SVM classifier uses rectangular images for HoG feature descriptor extraction and training.  ...  This improved version of HoG, bitmap-HoG (bHoG) hereafter in this paper, improves descriptor's length and thus the computational cost and speed of descriptor computation.  ... 
doi:10.5281/zenodo.159922 fatcat:eyu2ue334vd4rpyi7k6d74e2zq

Practical Methods for Vehicle Speed Estimation Using a Microprocessor-Embedded System with AMR Sensors

Vytautas Markevicius, Dangirutis Navikas, Adam Idzkowski, Darius Andriukaitis, Algimantas Valinevicius, Mindaugas Zilys
2018 Sensors  
The results of the evaluated speed and the execution time of the program code are presented for each method based on a dataset of 200 randomly driven vehicles.  ...  The result depends on the accepted threshold and the sampling frequency of both signals. The precision of the estimated result can be improved by using linear interpolation.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/s18072225 pmid:29996564 pmcid:PMC6069105 fatcat:leq2znl5m5ccrgw7y464l7aqoa

Fractal Image Compression on MIMD Architectures II: Classification Based Speed-up Methods

Jutta Hammerle, Andreas Uhl
2000 Journal of Computing and Information Technology  
In this paper we discuss parallel fractal image compression algorithms suited for MIMD architectures which employ block classification as speed-up method.  ...  Since fractal image compression is computationally very expensive, speed-up techniques are required in addition to parallel processing in order to compress large images in reasonable time.  ...  The following parameters determine the efficiency of parallel precalculations: number of PEs, speed of PEs, communication cost, complexity of precalculations, size of the image, and amount of overlap of  ... 
doi:10.2498/cit.2000.01.06 fatcat:drdrr3snj5bphby774kesjl3oq

Speeding up whole-genome alignment by indexing frequency vectors

T. Kahveci, V. Ljosa, A. K. Singh
2004 Bioinformatics  
A space-efficient index is computed for one string, and the second string is compared with this index in order to prune substring pairs that do not contain similar regions.  ...  Motivation: Many biological applications require the comparison of large genome strings. Current techniques suffer from high computational and I/O costs.  ...  ACKNOWLEDGEMENTS This work was supported in part by grants EIA-0080134 and DBI-0213903 from the National Science Foundation.  ... 
doi:10.1093/bioinformatics/bth212 pmid:15073002 fatcat:qdyis5f6efe2tgo6uloikwf4va

Towards High-Speed Vision for Attention and Navigation of Autonomous City Explorer (ACE) [chapter]

Tingting Xu, Tianguang Zhang, Kolja Khnlenz, Martin Buss
2008 Computer Vision  
Thereby, large and complex dynamically changing environments are perceived flexibly and efficiently. The detailed description of the camera platform is in (Kühnlenz, 2006a; Kühnlenz, 2006b) .  ...  It helps ACE determine the relatively precise position and orientation. Image processing at high frequency can decrease the time delay of close-loop control and improve the system stability.  ...  Memory The memory access is also a focus for an efficient programming on GPU.  ... 
doi:10.5772/6164 fatcat:teajsh76pfgofja5dwqcoikmam
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