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SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads

Islam Atta, Pinar Tozun, Anastasia Ailamaki, Andreas Moshovos
2012 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture  
SLICC is a programmer transparent, low cost technique to minimize instruction cache misses when executing OLTP workloads.  ...  OLTP workloads are known to have large instruction footprints that foil existing L1 instruction caches resulting in poor overall performance.  ...  Acknowledgments We thank the members of the AENAO and DIAS laboratories, Adrian Popescu, the reviewers, and Jared Smolens for their comments and help.  ... 
doi:10.1109/micro.2012.26 dblp:conf/micro/AttaTAM12 fatcat:n23rcbna2ncbvkdegutmuuhdyq

Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability

Lucia G. Menezo, Valentin Puente, Jose-Angel Gregorio
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
With a directory capable of tracking just 40% of the blocks kept in private caches, this coherence protocol is able to match the performance and energy of a sparse-directory capable of tracking 160% of  ...  With only 5% of tracked private cache entries, the average performance degradation of this construct is less than 8% compared to a 160% over-provisioned sparse-directory.  ...  ACKNOWLEDGMENTS The authors would like to thank the reviewers for their helpful comments. Special thanks to Dan Sorin and Viji Srinivasan for their valuable suggestions.  ... 
doi:10.1109/hpca.2015.7056033 dblp:conf/hpca/MenezoPG15 fatcat:4lssxzd2ozdf7eonk44s3dmsge

Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün
Therefore, this chapter initially proposes SLICC (Self-Assembly of Instruction Cache Collectives), a hardware technique that utilizes thread migration to minimize instruction misses for OLTP workloads.  ...  Self-Assembly of Instruction Cache Collectives (Q2) Are the current cache contents useful to this thread and for how long?  ...  Conclusions Conclusions OLTP workloads suffer from high instruction miss stalls on high-end server processors since their transaction instruction footprints are by far larger than current L1-I caches  ... 
doi:10.5075/epfl-thesis-6411 fatcat:6nr2j3f7jvdv7gwoaexy67xsda