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Domain-Specific Multi-Level IR Rewriting for GPU [article]

Tobias Gysi, Christoph Müller, Oleksandr Zinenko, Stephan Herhut, Eddie Davis, Tobias Wicky, Oliver Fuhrer, Torsten Hoefler, Tobias Grosser
2020 arXiv   pre-print
In essence, multi-level rewriting promises to herald the age of specialized compilers composed from domain- and target-specific dialects implemented on top of a shared infrastructure.  ...  In particular, we develop a prototype compiler and design stencil- and GPU-specific dialects based on a set of newly introduced design principles.  ...  ACKNOWLEDGEMENTS We thank Jean-Michel Gorius for his foundational stencil compiler work and the continuous support of our project.  ... 
arXiv:2005.13014v2 fatcat:3kjj5bdukbemte6yf4zgeq7spq

Code generation approaches for parallel geometric multigrid solvers

Harald Köstler, Marco Heisig, Nils Kohl, Sebastian Kuckuk, Martin Bauer, Ulrich Rüde
2020 Analele Stiintifice ale Universitatii Ovidius Constanta: Seria Matematica  
In contrast to manual implementations in a general-purpose computing language, they allow to integrate automatic code transforms to produce efficient code for different models and platforms.  ...  AbstractSoftware development for applications in computational science and engineering has become complex in recent years.  ...  Exascale Computing" through the projects TerraNeo and ExaStencils.  ... 
doi:10.2478/auom-2020-0038 fatcat:rr63bsabc5cbbbcw7eljtr3gzy

AN5D: automated stencil framework for high-degree temporal blocking on GPUs

Kazuaki Matsumura, Hamid Reza Zohouri, Mohamed Wahib, Toshio Endo, Satoshi Matsuoka
2020 Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization  
Stencil computation is one of the most widely-used compute patterns in high performance computing applications.  ...  We achieve the highest performance reported so far for all evaluated stencil benchmarks on the state-of-the-art Tesla V100 GPU.  ...  Computational resource of AI Bridging Cloud Infrastructure (ABCI) provided by National Institute of Advanced Industrial Science and Technology (AIST) was used.  ... 
doi:10.1145/3368826.3377904 dblp:conf/cgo/MatsumuraZWEM20 fatcat:x2y7cxwhw5c4tma5tjy44e6oey

High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit Numerical Solvers

Kamalavasan Kamalakkannan, Gihan R. Mudalige, Istvan Z. Reguly, Suhaib A. Fahmy
2021 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)  
This paper presents a workflow for synthesizing near-optimal FPGA implementations of structured-mesh based stencil applications for explicit solvers.  ...  We discuss determinants for a given stencil code to be amenable to FPGA implementation, providing insights into the feasibility and profitability of a design and its resulting performance.  ...  Most recent works utilize HLS tools, usually compiling OpenCL, and target both 2D and 3D stencil applications.  ... 
doi:10.1109/ipdps49936.2021.00117 fatcat:l72imzolbresvdhtamaxaxhniu

Automatic Generation of Interpolants for Lattice Samplings: Part II -- Implementation and Code Generation [article]

Joshua Horacsek, Usman Alim
Our design provides a handful of parameters for a practitioner to tune - this is one of the avenues that provides us with the flexibility to target many different computational architectures and tune performance  ...  We decompose the final algorithm from Part I and translate the resulting components into LLVM-IR (a low level language that can be compiled to various targets/architectures).  ...  Another example of numerical computation domain specific compiler (and language) is SDSLc, a language for generating fast stencil computation code [Rawat et al. 2015 ] -curiously, this work does not acknowledge  ... 
doi:10.48550/arxiv.2102.08518 fatcat:thw3sdmrwvh3fmtsxcgzbdyvmi