11 Hits in 4.2 sec

SCA Secure and Updatable Crypto Engines for FPGA SoC Bitstream Decryption

Florian Unterstein, Nisha Jacob, Neil Hanley, Chongyan Gu, Johann Heyszl
2019 Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop - ASHES'19  
cores and updates of the decryption engine.  ...  Unfortunately, with most currently available FPGAs and FPGA SoCs, it is difficult to use alternative cryptographic engines within the FPGA logic for this core functionality of bitstream decryption.  ... 
doi:10.1145/3338508.3359573 dblp:conf/ccs/UntersteinJHGH19 fatcat:aodlbsudffc7jlrln3rigee2fa

SCA secure and updatable crypto engines for FPGA SoC bitstream decryption: extended version

Florian Unterstein, Nisha Jacob, Neil Hanley, Chongyan Gu, Johann Heyszl
2020 Journal of Cryptographic Engineering  
A secure update of hardware functionality can in general be achieved by using built-in cryptographic engines and provided secret key storage.  ...  To solve this, we propose a comprehensive concept that uses an alternative and side-channel protected cryptographic engine within the FPGA logic instead of the built-in one for the crucial task of bitstream  ...  Unfortunately, with most currently available FPGAs and FPGA SoCs, it is difficult to use alternative cryptographic engines within the FPGA logic for this core functionality of bitstream decryption.  ... 
doi:10.1007/s13389-020-00247-2 fatcat:xgnl4djeznckzatufxling2ywq

SafeDB: Spark Acceleration on FPGA Clouds with Enclaved Data Processing and Bitstream Protection

Han-Yee Kim, Rohyoung Myung, Boeui Hong, Heonchang Yu, Taeweon Suh, Lei Xu, Weidong Shi
2019 2019 IEEE 12th International Conference on Cloud Computing (CLOUD)  
The AES key shared between FPGA and client for the bitstream encryption is generated in hard-wired logic using PKI and ECC.  ...  SafeDB provides a comprehensive and systematic hardware-based security framework from the bitstream protection to data confidentiality, especially for the cloud environment.  ...  For security, FPGA takes encrypted data, decrypts it, executes the kernel and finally encrypts the output for passing it externally.  ... 
doi:10.1109/cloud.2019.00029 dblp:conf/IEEEcloud/KimMHYSXS19 fatcat:qnoaeivkmrbnrgq3mw6wppo2ry

Foundations of Secure Scaling (Dagstuhl Seminar 16342)

Lejla Batina, Swarup Bhunia, Patrick Schaumont, Jean-Pierre Seifert, Marc Herbstritt
2017 Dagstuhl Reports  
While scaling is generally thought of as beneficial to the resulting implementations, this does not hold for secure electronic design.  ...  Indeed, the relations between scaling and the resulting security are poorly understood.  ...  We would like to evaluate the physical security of crypto across integration and technology. We consider two cases: 1. cache attacks ,2. fault injection attacks.  ... 
doi:10.4230/dagrep.6.8.65 dblp:journals/dagstuhl-reports/BatinaBSS16 fatcat:qya6rznvonbi7pfic7ocbxwkea

[Front matter]

2020 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)  
Past and potential TPC members outline their top ten topics of expertise in hardware and systems security.  ...  The keynote, visionary, and panels take place live on its "main stage" for the most seamless experience for both speakers and attendees.  ...  FPGA Bitstream Camouflaging Speaker: Geraldine Shirley Nicholas, UNCC Abstract Reconfigurable logic enables architectural updates for embedded devices by providing the ability to reprogram partial or  ... 
doi:10.1109/host45689.2020.9300269 fatcat:nruhx3qym5evvpk3bbki7pvfdq

An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications

Philippe Manet, Daniel Maufroid, Leonardo Tosi, Gregory Gailliard, Olivier Mulertt, Marco Di Ciano, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba, Pol Cuvelier (+2 others)
2008 EURASIP Journal on Embedded Systems  
For low-volume applications like in professional electronics applications, FPGA are used in combination with DSP and GPP in order to reach the performances required by the product roadmaps.  ...  This paper evaluates the interest and limitations when using DPR in professional electronics applications and provides guidelines to improve its applicability.  ...  For those applications, it is not possible to use a static design. The ICAP performances For industrial and security reasons, the bitstreams need to be encrypted.  ... 
doi:10.1155/2008/367860 fatcat:dxk7xje2lrfovelikyp57iwirm

Field Programmable Gate Array Applications—A Scientometric Review

Juan Ruiz-Rosero, Gustavo Ramirez-Gonzalez, Rahul Khanna
2019 Computation  
These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers' navigation systems  ...  Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science).  ...  FPGAs' research in this area covers FPGAs' vulnerabilities to SCA [326-328], security resistant designs against SCA [329-334] and hardware Trojan detection[335][336][337].  ... 
doi:10.3390/computation7040063 fatcat:wxtatzsvvnfopghdfl25hcfc2a

Trusted SoC Realization for Remote Dynamic IP Integration

Nadir Muhammad Khan
Heutzutage bieten field-programmable gate arrays (FPGAs) enorme Rechenleistung und Flexibilität.  ...  In dieser Arbeit wird ein Pay-per-Use-Lizenzierungsschema vorgeschlagen und unter Verwendung eines security framework (SFW) realisiert, um all diese Herausforderungen anzugehen.  ...  The internal cryptographic hardware engine is typically used for decryption and authentication. Therefore, Secure Boot is considered resistant against SCAs as well.  ... 
doi:10.5445/ir/1000140875 fatcat:iti34xew4ndpnb6cxhtadoljzq

Securing Embedded Digital Systems For In-Field Applications

Mario Barbareschi
The FPGA programming process is accomplished by a configuration file, so called bitstream and hacking attempts can succeed in either cloning the bitstream or, by means of reverse engineering techniques  ...  , fast time-to-market, and low overall non-recurring engineering costs (NRE), but they almost lack in providing security mechanisms to protect intellectual properties (IPs) configured on them.  ...  The same key has to be programmed into the FPGA device in order to allow the dedicated hard-wired crypto-engine to eventually decrypt ciphered bitstreams before write it in the configuration memory.  ... 
doi:10.6092/unina/fedoa/10320 fatcat:v2xztsirxvcqvncrodyebubtnm

A Work Life Balance of Employees and Its Effect on Emotional Intelligence

2019 Zenodo  
This study is based on the responses of teaching staffs both men and woman from primary schools. Research instrument designed on the basis of literature survey and then data was collected.  ...  This study may give insight regarding the relationship between work life balance and emotional intelligence.  ...  A Study on issue related to Self-Help Groups in India Rozy garg  Abstract: A SHG is an informal association to enhance the member's financial security as primary focus and other common interest of members  ... 
doi:10.5281/zenodo.5476173 fatcat:5rro63pefzbpxigfgnilhazy5a

Dagstuhl Reports, Volume 6, Issue 8, August 2016, Complete Issue [article]

In this work, the target FPGA use soft PUFs for key storage and DPA-resistant decryptor for bitstream decryption.  ...  At each power-on of the FPGA in the untrusted environment, the encrypted bitstream is transferred to the FPGA from the NVM and it is decrypted using the embedded key.  ...  Issues when working with a pan-genome defined by a global coordinate system is the ability to map between different coordinate systems and to update it (see below).  ... 
doi:10.4230/dagrep.6.8 fatcat:jhbruchpmvdthoe45w75w35wpe