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FPGA-based design of an evolutionary controller for collision-free robot navigation
2003
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03
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The employment of field programmable gate arrays (FPGAs) to a robot controller is very attractive, since it allows for fast IC prototyping and low cost modifications. ...
The purpose of this study is to design a FHT which utilizes less hardware resources as compared to the existing designs and also suggest means for reducing the input length of the Walsh sequence. ...
The CAC can be used either for Field
Programmable Analog Array (FPAA) or for Field Programmable Digital-Analog Mixed Array (FPMA). ...
doi:10.1145/611817.611852
dblp:conf/fpga/AzharD03
fatcat:juups7gn3ve2vhw2fbicwvt5kq
Lattice adaptive filter implementation for FPGA
2003
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03
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The employment of field programmable gate arrays (FPGAs) to a robot controller is very attractive, since it allows for fast IC prototyping and low cost modifications. ...
The purpose of this study is to design a FHT which utilizes less hardware resources as compared to the existing designs and also suggest means for reducing the input length of the Walsh sequence. ...
The CAC can be used either for Field
Programmable Analog Array (FPAA) or for Field Programmable Digital-Analog Mixed Array (FPMA). ...
doi:10.1145/611817.611877
dblp:conf/fpga/PohlMKTL03
fatcat:vg523unfzvcmvl2rsw4ja3ksma
Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies
2009
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A significant demand for embedded high-performance WiMAX solutions is forcing designers to seek single-chip multicore systems that offer competitive advantages in terms of all performance metrics, such ...
reconfigurable (DR) processors are proving to be strong candidates for processing cores in future highperformance multicore-processor systems. ...
WiMAX Implementations Today, many WiMAX implementations have emerged based on different technologies including ASICs, field-programmable gate arrays (FPGAs), and multicore processors. ...
doi:10.1109/tcad.2009.2032361
fatcat:mc6eflr6onef5oufokurvqknya
Intelligent metaphotonics empowered by machine learning
2022
Opto-Electronic Advances
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Artificial intelligence and machine learning penetrate rapidly into the fundamental physics of light, and they provide effective tools for the study of the field of metaphotonics driven by optically induced ...
These novel approaches underpin the fundamental principles of lightmatter interaction developed for a smart design of intelligent photonic devices. ...
A.B. acknowledges a support from the Foundation for the Advancement of Theoretical Physics and Mathematics "BASIS ". ...
doi:10.29026/oea.2022.210147
fatcat:yx47l4ia4fgmbpkkcmp5oszg7a
Intelligent metaphotonics empowered by machine learning
[article]
2021
arXiv
pre-print
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light-matter interaction developed for a smart design of intelligent photonic devices. ...
Concepts and approaches of artificial intelligence and machine learning penetrate rapidly into the fundamental physics of light, and they provide effective tools for the study of the field of metaphotonics ...
A.B. acknowledges a support from the Foundation for the Advancement of Theoretical Physics and Mathematics "BASIS". A.T. acknowledges a support from the Australian Research Council Grant No. ...
arXiv:2110.11618v1
fatcat:xewcojcx75dthgughccsgteyvu
Logic Synthesis
[chapter]
2017
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology
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ACKNOWLEDGMENT e authors thank Vladimir Yutsis for his helpful feedback on Section 1.5.2. ...
high-level synthesis, in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2014, pp. 199-208. 51. ...
., Chortle: A technology mapping program for lookup tablebased �eld-programmable gate arrays, in Proceedings of the Design Automation Conference, 1990, pp. 613-619. 71. ...
doi:10.1201/9781315215112-13
fatcat:me52zpnxyfcczh3choo2p4zulm
Modeling, analysis and exploration of layers: A 3D computing architecture
2014
2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)
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Acknowledgements This thesis is the result of my work as research assistant at the Institute for Communication Technologies and Embedded Systems (ICE), Multiprocessor System-on-Chip Architectures (MPSoC ...
Field-programmable Gate Array (FPGA)-based designs for SDR, like the WARP board, are extensively used for prototyping and research of new wireless standards and optimizations [71] [153] , but power ...
The challenge of exploring the huge design space offered by reconfigurable computing via high-level abstraction tools has not yet been solved. ...
doi:10.1109/vlsi-soc.2014.7004167
dblp:conf/vlsi/Rakossy14
fatcat:6h3w3hfgdjeytitl7wnwrard34
Present State of CFD Softwares Application for Launch Vehicle Analysis
발사체 해석을 위한 CFD 소프트웨어 적용 현황
2020
Journal of the Korean Society of Propulsion Engineers
발사체 해석을 위한 CFD 소프트웨어 적용 현황
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This software program takes an XML representation of the contents of a Hierarchical Data Format-Earth Observing System (HDF-EOS) file and recreates the file from that description . ...
Please visit the following URL for additional information: http://opensource .gsfc .nasa .gov/projects/xml2he/index . ...
The target IP core is a VHDL description suitable for implementation in a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) .
U.S. ...
doi:10.6108/kspe.2020.24.3.071
fatcat:trxkhiuqrjakll32bcjxskgwju
To the Editor
2017
Pain medicine (Malden, Mass.)
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Acknowledgments The authors thank colleagues in the Simulation and Visualization Group, Department of Computer Science, University of Hull for valuable discussions and technical assistance. ...
JGE acknowledges funding from the University of Hull in support of his PhD studies. We thank the reviewers for their valuable comments.
Acknowledgements This work is part-funded by DSTL. ...
Therefore, designers can utilise XCD to easily explore different design solutions for architectural designs. ...
doi:10.1093/pm/pnx150
pmid:29016898
fatcat:pao75lxgbvg3hkyhod262f5ebe
Design and Verification Environment for High-Performance Video-Based Embedded Systems
[chapter]
2014
Distributed Embedded Smart Cameras
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In this dissertation, a method and a tool to enable design and verification of computation demanding embedded vision-based systems is presented. ...
We also propose a novel streaming interface, called Component Interconnect and Data Access (CIDA), for embedded video designs, along with a formal model and a component composition mechanism to cluster ...
Field programmable gate arrays (FPGA). ...
doi:10.1007/978-1-4614-7705-1_4
fatcat:wx73qh32mrekfg2poxusgkfwya
DeSyRe: On-demand system reliability
2013
Microprocessors and microsystems
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In this context, DeSyRe delivers a new generation of systems that are reliable by design at wellbalanced power, performance, and design costs. ...
In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. ...
Xentium DSP The Xentium core is a 32-bit fixed-point DSP core designed for high-performance embedded signal processing. ...
doi:10.1016/j.micpro.2013.08.008
fatcat:jg623r4hmngthk652u7qi6ibme
Quantum Computing: A Taxonomy, Systematic Review and Future Directions
[article]
2021
arXiv
pre-print
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Quantum computing is a highly topical and fast-moving field of research with significant ongoing progress in all facets. ...
A detailed overview of quantum software tools and technologies, post-quantum cryptography and quantum computer hardware development to document the current state-of-the-art in the respective areas. ...
BACKGROUND The basic building blocks of a large-scale quantum computer, as shown in Figure 4 , consist of a quantum central processing unit, quantum gates, quantum control and measurement circuitry, quantum ...
arXiv:2010.15559v4
fatcat:y6cuttww5fd5jdmvcer352lh4e
Program
2021
2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW)
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A non-
overlapped implanted (NOI) non-volatile memory device is used as a synaptic unit. The NOI array is
designed to form a convolutional neural network. ...
Structured by gate recurrent unit (GRU), this paper proposes a new predict model with the
combination of trajectory mapping method. ...
doi:10.1109/icce-tw52618.2021.9602919
fatcat:aetmvxb7hfah7iuucbamos2wgu
Formal hardware specification languages for protocol compliance verification
2004
ACM Transactions on Design Automation of Electronic Systems
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One of the central tools in any verification project is the modeling language, and we survey the field of candidate languages for protocol compliance verification, limiting our discussion to languages ...
originally intended for hardware and software design and verification activities. ...
Researchers use the language in developing and verifying designs based on Field Programmable Gate Arrays (FPGAs) for applications such as high-performance graphics, digital signal processing in high-speed ...
doi:10.1145/966137.966138
fatcat:hffgv4stqnhlxohm4ojyuu3lfq
Space and High Energy Experiments Advanced Electronic Systems 2012
2012
International Journal of Electronics and Telecommunications
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A digest of Wilga references is presented [1]-[60]. This paper is the first part of the digest focused on astronomy, space, astroparticle physics, accelerators, and high energy physics experiments. ...
It is also a great occasion for SPIE, IEEE, OSA and PSP students to meet together in a large group spanning the whole country with guests from this part of Europe. ...
Instead of using a CPU a GPU (graphical processing unit) was used for performing parallel computations on the spectral characteristics. ...
doi:10.2478/v10177-012-0060-0
fatcat:2nrsjwpharcuva4642wi3zmbim
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