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S/390 microprocessor design
2000
IBM Journal of Research and Development
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The technical, business, and market requirements for large enterprise servers ("mainframes") strongly influence the design of microprocessors for these systems. ...
The requirements for robust, scalable performance across a wide range of workloads, highly efficient logical partitioning, and very high hardware reliability affect the cache structure, internal code, ...
Error detection and recovery The use of S/390 systems for enterprise-scale missioncritical applications places a premium on all aspects of system reliability, availability, and serviceability. ...
doi:10.1147/rd.446.0899
fatcat:dy4d5vrqjfagjceuzpe5xzgnt4
S/390 cluster technology: Parallel Sysplex
1997
IBM Systems Journal
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System model. An S/390 Parallel Sysplex!" ...
The S/390 Par- allel Sysplex architecture is generally characterized as a Shared-data model. ...
doi:10.1147/sj.362.0172
fatcat:ggd2f6u5qvhypgys6lwwflpvhe
Cluster architectures and S/390 Parallel Sysplex scalability
1997
IBM Systems Journal
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It also provides for effective dynamic load balancing, high data buffer hit ratios, and load balancing after a failure. ...
We quantify the scalability of the SI390 Parallel Sysplex and show that the transaction rate supported is close to linear as nodes are added to the system. ...
on the S/390 Parallel Sysplex architecture. ...
doi:10.1147/sj.362.0221
fatcat:rp3f375iyjhcrnt7gucaowsroq
A 400-MHz S/390 microprocessor
1997
IEEE Journal of Solid-State Circuits
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A microprocessor implementing IBM S/390 architecture operates in a 10 + 2 way system at frequencies up to 411 MHz (2.43 ns). ...
A phase-locked-loop (PLL) provides a processor clock that runs at 22 the system bus frequency. ...
The robust checking and recovery mechanism is crucial in the mission-critical enterprise-wide server applications of S/390 systems, where customers expect and rely on "bulletproof" design to protect their ...
doi:10.1109/4.641686
fatcat:qkufxt4n4faulikavu6aqxoijm
Fiber optic interconnects for the IBM S/390 Parallel Enterprise Server G5
1999
IBM Journal of Research and Development
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With the introduction of the Generation 5 Parallel Enterprise Server in May 1998, a number of important new fiber optic features and enhancements to existing features were made available for applications ...
a new type of small-form-factor fiber optic connector, and the Geographically Dispersed Parallel Sysplex using the 9729 Optical Wavelength Division Multiplexer. ...
The test system used a bipolar S/390 mainframe as the site A processor, and a CMOS Generation 5 server as the site B processor. ...
doi:10.1147/rd.435.0807
fatcat:vvbuco5c75hz5c6wpxmf5tw4tq
Multimedia file serving with the OS/390 LAN Server
1997
IBM Systems Journal
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At each of these schools the server is an S/390 Enterprise Server Model 9672-R42 with MVS Release 5.2.2 or 0/390 Release 1. ...
The streaming capacity of the OS/390 LAN Server can be up to a thousand streams, depending on the stream rate and the speed and the number of processors of the S/390 system deployed as servers. ...
doi:10.1147/sj.363.0374
fatcat:hguhzs334jfqdmilpnur7yb5wq
Technical note: IMS celebrates thirty years as an IBM product
1998
IBM Systems Journal
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The IMS mul- tiaddress space architecture exploits the multipro- cessing architecture of MVS and the transformation of the s/390 platform to the s/390 Parallel Enterprise Server*. ...
The resource managers can also exploit the coupling facility cache structures for database buffer manage-
BLACKMAN §01
Figure 2 _IMS Version 6 in an S/390 Parallel Sysplex
IMS WEB CLIENT
IMS IN A PARALLEL ...
doi:10.1147/sj.374.0596
fatcat:4lr4vvidijckzj2hnwviw6n3pi
Multimedia resource management in OS/390 LAN Server
1997
IBM Systems Journal
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A. Dan, M. Kienzle, and D. Sitaram, “Dynamic Policy of Seg- ment Replication for Load-Balancing in Video-on-Demand Servers,” ACM Multimedia Systems 3, No. 3, 93-103 (July 1995).
. A. Dan and D. ...
Stephen Dulin JBM S/390 Division, 522 South Road, Poughkeep- sie, New York 12601 (electronic mail: sdulin@vnet.ibm.com). Mr. ...
doi:10.1147/sj.363.0393
fatcat:rfjpahhho5effmpasesmwu7e54
First- and second-level packaging for the IBM eServer z900
2002
IBM Journal of Research and Development
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This server contains the world's most complex multichip module (MCM), with a wiring length of 1 km and a maximum power of 1300 W on a glass-ceramic substrate. ...
Similarly, two different board technologies for the housing of the CEC are discussed, and the impact of their electrical properties on the system design is described. ...
Endicott, and of the Hitachi packaging department in Hadano. ...
doi:10.1147/rd.464.0397
fatcat:6skl6bea2bhc3pzhub2pmzsvmu
RAS design for the IBM eServer z900
2002
IBM Journal of Research and Development
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From the RAS perspective, the longstanding RAS strategy for the IBM S/390 ® and now the zSeries has provided an excellent foundation for self management. ...
This paper describes the z900 RAS enhancements and how they strengthen the RAS strategy building blocks and provide a basis for autonomic computing. ...
Acknowledgments The authors would like to recognize the other members of the zSeries RAS Council for their support and contribution in pursuing/delivering the highest RAS ...
doi:10.1147/rd.464.0503
fatcat:aqhp5cgxf5bfdojamk4lodmg4m
High performance CMOS circuit techniques for the G-4 S/390 microprocessor
Proceedings International Conference on Computer Design VLSI in Computers and Processors
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This paper describes the CMOS circuit techniques used in the design of the high performance Generation-4 S/390 microprocessor. ...
The on-chip L1 cache was designed extensively with selfresetting CMOS (SRCMOS) circuitry to provide a 2.0 ns access time and up to 500 MHz operation. ...
Introduction A single chip CMOS microprocessor was designed for the IBM S/390 Enterprise Server Generation-4 system with the goal of replacing the earlier ES/9000 bipolar-based systems. ...
doi:10.1109/iccd.1997.628875
dblp:conf/iccd/WarnockSCC97
fatcat:znldyu3xf5bhzhlcflh257xwva
Functional verification of the z990 superscalar, multibook microprocessor complex
2004
IBM Journal of Research and Development
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Since the methods used at system-level verification were much the same as the ones used on the CMOS-based IBM S/390 Parallel Enterprise Server G4, the focus of this paper is on the work done at the unit ...
After successfully completing element stress testing, the components were combined and verified at the system level. ...
Acknowledgments The authors acknowledge all z990 design team members and other individuals throughout IBM for their contributions to the verification effort. ...
doi:10.1147/rd.483.0347
fatcat:c7pqoghcxzawbpgskfqe3jvs4y
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
2002
IBM Journal of Research and Development
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The approach was hierarchical, based on but considerably expanding the practice used for verification of the CMOS-based IBM S/390 Parallel Enterprise Server TM G4. ...
Sim farm A massive simulation infrastructure was required to simulate a processor and system of this size and sophistication. ...
The hierarchical verification approach expanded the practice used on the CMOS S/390 Parallel Enterprise Server* G4 system [1] . ...
doi:10.1147/rd.461.0053
fatcat:474llttpkvghngwg4q6veuhvqq
IBM Parallel Sysplex clustering: Technology options for continuous availability
2008
IBM Systems Journal
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CITED REFERENCES AND NOTES 1. The IBM Systems Journal 36, No. 2, 1997, issue was devoted to “S/390 Parallel Sysplex Cluster” and provides a good background to IBM Parallel Sysplex.
N. S. Bowen, J. ...
Cache model—Provides global coherency controls for distributed local server caches and a high- performance shared data cache.
¢ List model—Provides a rich set of queuing constructs in support of workload ...
doi:10.1147/sj.2008.5386514
fatcat:byqwphamabadrohxc5odtfjoue
IBM POWER7 multicore server processor
2011
IBM Journal of Research and Development
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A new memory interface using buffered double-data-rate-three DRAM and improvements in reliability, availability, and serviceability are discussed. ...
The IBM POWER A processor is the dominant reduced instruction set computing microprocessor in the world today, with a rich history of implementation and innovation over the last 20 years. ...
The balanced design allows the processor to scale from a single socket low-end blade to a high-end enterprise system with 32 sockets, 256 cores, and 1024 threads. ...
doi:10.1147/jrd.2011.2127330
fatcat:kztcasllyvgs5cuvzyf54myeyy
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