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Run-Time Accessible DRAM PUFs in Commodity Devices
[chapter]
2016
Lecture Notes in Computer Science
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This paper is the first to enable the run-time access of decay-based intrinsic DRAM PUFs in commercial off-the-shelf systems, which requires no additional hardware or FPGAs. ...
Finally, we introduce lightweight protocols for device authentication and secure channel establishment, that leverage the DRAM PUFs at run-time. ...
The authors would like to thank Kevin Ryan and Ethan Weinberger for their help with building the heater setup used in the experiments, and Intel for donating the Intel Galileo boards used in this work. ...
doi:10.1007/978-3-662-53140-2_21
fatcat:3tpuyvnymvg4tfnpqzjz7fkjp4
Intrinsic Physical Unclonable Function (PUF) Sensors in Commodity Devices
2019
Sensors
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It can be difficult to implemented in commercial off-the-shelf devices. ...
Furthermore, we configured the DRAM PUF-based sensor in a DRAM PUF-based key generation scheme which improves the practicability of the design. ...
Acknowledgments: We would like to thank Jakub Szefer and Wenjie Xiong for guidance and help with the PUF implementation on Rpi. ...
doi:10.3390/s19112428
fatcat:tded54czafff3mkm7vzr23oqfi
Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins
[article]
2021
arXiv
pre-print
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This dissertation rigorously characterizes many modern commodity DRAM devices and shows that by exploiting DRAM access timing margins within manufacturer-recommended DRAM timing specifications, we can ...
Second, we find that we can uniquely identify DRAM devices by the locations of failures that result when we access DRAM with timing parameters reduced below specification values. ...
PUF without modifying commodity DRAM devices, 2) introduce an effective DRAM PUF that is runtime-accessible at all operating temperatures, 3) demonstrate a wide variety of tradeoffs in DRAM PUFs, based ...
arXiv:2109.14520v1
fatcat:7hhrlz3tfjgx5fekdblfawxf3a
Dataplant: Enhancing System Security with Low-Cost In-DRAM Value Generation Primitives
[article]
2019
arXiv
pre-print
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Second, a new cold boot attack prevention mechanism that automatically destroys all data within DRAM on every power cycle with zero run-time energy and latency overheads. ...
Using a combination of detailed simulations and experiments with 136 real commodity DRAM chips, we show that our Dataplant-based PUF has 1.8x higher throughput than the best state-of-the-art DRAM PUFs. ...
We customize Ramulator [76] to support all the mechanisms on in-order cores. ...
arXiv:1902.07344v2
fatcat:rpfx6htqjfbhtjirzjy76rbbia
Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security †
2018
Cryptography
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In this work, we extend the work of Schaller et al. by presenting a run-time accessible implementation of this PUF and by further reducing the time required for the generation of its responses. ...
Physical Unclonable Functions (PUFs) based on the retention times of the cells of a Dynamic Random Access Memory (DRAM) can be utilised for the implementation of cost-efficient and lightweight cryptographic ...
Run-Time Row Hammer PUF Implementations in Commodity DRAM In this section, we examine in detail the different parameters and factors that can affect the operation of a Row Hammer PUF. ...
doi:10.3390/cryptography2030013
fatcat:ec6iyndbpfdkreqa27aj53ewna
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
[article]
2021
arXiv
pre-print
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To overcome these limitations, we propose enabling programmable DRAM internal timings for controlling in-DRAM components. ...
DRAM executes the given commands using internal components (e.g., access transistors, sense amplifiers) that are orchestrated by DRAM internal timings, which are fixed foreach DRAM command. ...
A much earlier version of this paper was placed on arXiv in February 2019 [113] . ...
arXiv:2106.05632v1
fatcat:57kx6f3cibckzgcbuz3dcbnosa
Fast DRAM PUFs on Commodity Devices
2020
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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only has root access for a lim- There are several difficulties inherent in implementing a 800 DRAM latency PUF on commodity hardware. ...
The PUF, at 735 least in the case of the proposed design, is a mean to authen-736 ticate devices, not a means in itself to secure the device from 737 illicit access. ...
doi:10.1109/tcad.2020.3012218
fatcat:oqjx2lby5bdf5hilt66hp4nmpq
An Overview of DRAM-Based Security Primitives
2018
Cryptography
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size, and the easy way in which they can be accessed, even at run-time. ...
Security primitives based on Dynamic Random Access Memory (DRAM) can provide cost-efficient and practical security solutions, especially for resource-constrained devices, such as hardware used in the Internet ...
This work has also been supported by Comcast Corporation, a company headquartered in Philadelphia, PA, USA, and Honeywell International Inc., a company headquarted in Morris Plains, NJ, USA. ...
doi:10.3390/cryptography2020007
fatcat:43ohhg2ctzhrzlv7msocufwg3e
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
[article]
2021
arXiv
pre-print
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We experimentally demonstrate that QUAC reliably generates random values across 136 commodity DDR4 DRAM chips from one major DRAM manufacturer. ...
QUAC-TRNG exploits the new observation that a carefully-engineered sequence of DRAM commands activates four consecutive DRAM rows in rapid succession. ...
Our goal in this work is to develop a TRNG that uses commodity DRAM devices to generate random numbers with both high throughput and low latency. ...
arXiv:2105.08955v2
fatcat:64w37n2ymbbapoe4x4v4dd4tpm
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput
[article]
2018
arXiv
pre-print
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We use our observations to develop D-RanGe, a methodology for extracting true random numbers from commodity DRAM devices with high throughput and low latency by deliberately violating the read access timing ...
To demonstrate that our TRNG design is viable using commodity DRAM chips, we rigorously characterize the behavior of activation failures in 282 state-of-the-art LPDDR4 devices from three major DRAM manufacturers ...
D-RaNGe runs entirely in software and is capable of immediately running on any commodity system that provides the ability to manipulate DRAM timing parameters within the memory controller [7, 8] . ...
arXiv:1808.04286v2
fatcat:32gvtbf56jclzh4sflno2g4cde
Improving Resilience by Deploying Permuted Code onto Physically Unclonable Unique Processors
2016
2016 Cybersecurity and Cyberforensics Conference (CCC)
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In this paper we propose the deployment of permuted code onto Physically Unclonable Unique Processors in order to resist common cyber attacks. ...
In: 2016 Cybersecurity and Cyberforensics Conference (CCC). IEEE, Piscataway, pp. 144-150. ISBN 9781509026579 , http://dx. ...
The data cache has direct read/write access to the DRAM, but the instruction cache accesses the DRAM via an inverse permutation unit. ...
doi:10.1109/ccc.2016.30
dblp:conf/ccc2/AssmuthCKRMVSFW16
fatcat:bsvx2xgydbafzlpyelncoimlau
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM
[article]
2021
arXiv
pre-print
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Several recent works have demonstrated PuM techniques in off-the-shelf DRAM devices. ...
Using PiDRAM, we implement and evaluate two state-of-the-art PuM techniques: in-DRAM (i) copy and initialization, (ii) true random number generation. ...
of reduced DRAM timing operations that are fundamental to enabling PuM in current DRAM devices. ...
arXiv:2111.00082v3
fatcat:xafmmdqxl5gi7hcmbtumotmrzq
A Modern Primer on Processing in Memory
[article]
2020
arXiv
pre-print
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At the same time, conventional memory technology is facing many technology scaling challenges in terms of reliability, energy, and performance. ...
This design choice goes directly against at least three key trends in computing that cause performance, scalability and energy bottlenecks: (1) data access is a key bottleneck as many important applications ...
Row Decoder
D-RaNGe Key Idea • A cell's latency failure probability is inherently related to random process variation from manufacturing D-RaNGe and the DRAM Latency PUF show that commodity DRAM devices ...
arXiv:2012.03112v1
fatcat:hq2i2xzq4nbszenq7rqmjzcjci
RowHammer: A Retrospective
[article]
2019
arXiv
pre-print
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It is the phenomenon that repeatedly accessing a row in a modern DRAM chip causes bit flips in physically-adjacent rows at consistently predictable bit locations. ...
This retrospective paper describes the RowHammer problem in Dynamic Random Access Memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 conference rowhammer-isca2014. ...
We have shown, in our ISCA 2014 paper [133] , the existence of disturbance errors in commodity DRAM chips that are sold and used in the field. ...
arXiv:1904.09724v1
fatcat:eucfr7lbrvawrjtztthuharb5a
AEGIS: A single-chip secure processor
2005
Information Security Technical Report
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We briefly assess the cost of the security mechanisms in our processor and show that it is reasonable. ª ...
This article presents the AEGIS secure processor architecture, which enables new applications by ensuring private and authentic program execution even in the face of physical attack. ...
manage VM (SSP cannot) TE mode: R/W access to verified memory Access to most security instructions PTR mode: R/W access to private memory Access to PUF instructions
Authentication Our processor allows ...
doi:10.1016/j.istr.2005.05.002
fatcat:fs4yl5r63ba5tlciuudzw67oha
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