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Inter-FPGA interconnect topologies exploration for multi-FPGA systems

Umer Farooq, Habib Mehrez, Muhammad Khurram Bhatti
2018 Design automation for embedded systems  
Prototyping using multi-FPGA systems offers significant advantages over simulation and emulation based pre-silicon verification techniques.  ...  Experimentation reveals that fully customized interconnect topology using a hybrid combination of direct two and multi point tracks gives the best frequency results for all the FPGA boards.  ...  Authors would also like to thank Zied Marrakchi and Hayder Mrabet from Flexras Technologies for their suggestions and guidance to enhance the quality of this work.  ... 
doi:10.1007/s10617-018-9207-2 fatcat:xfehs7lnxvbinbg5nbtzds4zwy

Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

A. Ye, J. Rose
2006 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper describes such an FPGA routing architecture, called the multi-bit routing architecture, which employs bus-based connections in order to exploit datapath regularity.  ...  It is experimentally shown that, comparing to conventional FPGA routing architectures, the multi-bit routing architecture can achieve 14% routing area reduction for implementing datapath circuits, which  ...  As a result, the router is forced to use bus-based tracks to route individual signals, which reduces the area efficiency of the multi-bit architecture past the 50% point.  ... 
doi:10.1109/tvlsi.2006.876095 fatcat:6owrflm27rhatgskjqnfkc375a

Fuzzy-based MPPT algorithm implementation on FPGA chip for multi-channel photovoltaic system

Hanen Abbes, Hafedh Abid, Kais Loukil, Mohamed Abid, Ahmad Toumi
2022 International Journal of Reconfigurable and Embedded Systems (IJRES)  
Therefore, this paper deals with the execution of the fuzzy-based maximum power point tracking (MPPT) technique by the means of the FPGA chip for a multi-channel photovoltaic system.  ...  In opposition to traditional controls, fuzzy logic based control presents more efficiency and reliability response for non-linear systems.  ...  In particular, the use of intelligent and complex maximum power point tracking (MPPT) control algorithms incites researchers to use FPGA.  ... 
doi:10.11591/ijres.v11.i1.pp49-58 fatcat:xmeym2mijvc4rnkhzgz3zia7ze

Static schedluing of multiple asynchronous domains for functional verification

Murali Kudlugi, Charles Selvidge, Russell Tessier
2001 Proceedings of the 38th conference on Design automation - DAC '01  
After formulating the scheduling problem and describing our general approach, a discussion of the integration of our algorithms with a commercial FPGA-based logic emulation system from Ikos Systems is  ...  These systems, which include logic emulators [6, 7, 8] and parallel cycle-based simulators, often contain special-purpose logic processors or FPGAs which evaluate logic and communicate results using a  ...  For logic emulation systems, inter-FPGA (processor) communication scheduling is based on the virtual clock.  ... 
doi:10.1145/378239.379040 dblp:conf/dac/KudlugiST01 fatcat:bbn66wwumvhtdizukjbbuhesb4

Towards scalable FPGA CAD through architecture

Scott Y.L. Chin, Steven J.E. Wilton
2011 Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '11  
We extend previous studies on logic block architectures by quantifying the area, delay and CAD runtime trade-offs for large capacity blocks, and also investigate some multi-level logic block architectures  ...  Long FPGA CAD runtime has emerged as a limitation to the future scaling of FPGA densities.  ...  This has opened up new markets for FPGAs since they can now implement more complex digital systems.  ... 
doi:10.1145/1950413.1950443 dblp:conf/fpga/ChinW11 fatcat:eu4z4ilkkbc4hplorpr2iomlsm

Manual clock distribution technique in partitioning stage for multi-FPGA prototyping

Salahuddin Savugathali, Muslim Mustapa, Fazrul Faiz Zakaria
2019 Indonesian Journal of Electrical Engineering and Computer Science  
A solution to prototyping multi-million logic gates of ASIC/SoC circuit into the FPGA platform for verification purpose is by partition the design into multi-FPGA.  ...  In this paper, <a name="_Hlk509759525"></a>Synopsys protocompiler tool will be used to perform the prototyping process of the large 4 core CPU based circuit into the HAPS-80 FPGA platform.  ...  In [13] , a proposed iterative routing algorithm in [14] is enhanced to route multi-terminal nets in multi-point tracks for routing cut nets in two point track by saving the FPGA [15] , author has  ... 
doi:10.11591/ijeecs.v14.i2.pp637-645 fatcat:mhzyei3ayjbdbhe3idwxcz4inu

L4: An FPGA-Based Accelerator for Detailed Maze Routing

John A. Nestor, Jeremy Lavine
2007 2007 International Conference on Field Programmable Logic and Applications  
This paper describes an FPGA-based accelerator for maze routing applications such as integrated circuit detailed routing.  ...  By time-multiplexing multiple layers over a two-dimensional array of processing elements, this approach can support multi-layer grids large enough for detailed routing while providing at 1-2 orders of  ...  INTRODUCTION Routing is a key part of the physical design of electronic systems.  ... 
doi:10.1109/fpl.2007.4380672 dblp:conf/fpl/NestorL07 fatcat:z3tidfxhgzg55d5jpjx5fnv4dm

Error-Rate Estimation Based on Multi-Signal Flow Graph Model and Accelerated Radiation Tests

Wei He, Yueke Wang, Kefei Xing, Wei Deng, Zelong Zhang, Jun Xu
2016 PLoS ONE  
In addition, an experimental method and accelerated radiation testing system for a signal processing platform based on the field programmable gate array (FPGA) is presented.  ...  A model for the system functional error rate (SFER) is proposed.  ...  Acknowledgments We would like to thank the Shanghai Aerospace Electronics Company Limited for the testing equipment they provided and their work in building the experimental system.  ... 
doi:10.1371/journal.pone.0161378 pmid:27583533 pmcid:PMC5008791 fatcat:xab7v3wwmreyhf7ulbcys4jnzm

Routing on field-programmable switch matrices

A. Ejnioui, N. Ranganathan
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We extend the switch matrix architecture proposed by Zhu et al. to route nets between FPGA chips in a multi-FPGA system.  ...  Index Terms-Field programmable gate arrays (FPGAs), interconnect structures, multi-FPGA systems, switch routing.  ...  in multi-FPGA systems [12] .  ... 
doi:10.1109/tvlsi.2003.810778 fatcat:eg2pdklovnb7jdgz2abgugn2zu

The roles of FPGAs in reprogrammable systems

S. Hauck
1998 Proceedings of the IEEE  
Reprogrammable systems based on field programmable gate arrays are revolutionizing some forms of computation and digital logic.  ...  As a custom-computing machine, they achieve the highest performance implementation for many types of applications.  ...  Another common inclusion in a multi-FPGA system is crossbars or FPIC's. For example, a multi-FPGA system with a crossbar or hierarchical crossbar topology requires chips purely for routing.  ... 
doi:10.1109/5.663540 fatcat:rrpdgyfqyzdcxdcplblk6gv42a

Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures

Asmeen Kashif, Mohammed A. S. Khalid
2016 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)  
All 2-point and multi-point inter-FPGA nets are routed in MFS point-to-point connections. Multi-terminal nets are split into several 2terminal nets.  ...  The second step routes the inter-FPGA nets according to the available physical tracks, I/O resources of the FPGA and the routing architecture of MFS.  ... 
doi:10.1109/mwscas.2016.7869975 dblp:conf/mwscas/KashifK16 fatcat:hgpls6pryvfvpnsbwnvxup6o34

A survey of DA techniques for PLD and FPGA based systems

R. Venkateswaran, P. Mazumder
1994 Integration  
Topics covered include logic synthesis for PLDs and FPGAs along with an in-depth survey of important technology mapping, partitioning and place and route algorithms for different FPGA architectures.  ...  In this article, we attempt to present in an unified manner, the different tools and their underlying algorithms using an example of a vending machine controller as an illustrative example.  ...  Partitioning for FPGAs More sophisticated algorithms are used to partition the larger systems designed using FPGAs.  ... 
doi:10.1016/0167-9260(94)90001-9 fatcat:o4mwhgj4rzglpf6r2nodsqiv74

SOCC 2019 Author Index

2019 2019 32nd IEEE International System-on-Chip Conference (SOCC)  
for FPGA High-Level Synthesis Orchard, Garrick T1A.2 318 EBBIOT: A Low-complexity Tracking Algorithm for Surveillance in IoVT Using Stationary Neuromorphic Vision Sensors Oszwald, Florian  ...  Fused Multiply-Add for Variable Precision Floating-Point Ne, Kyaw Zwa Lwin W2A.3 86 Reconfigurable Routing Paths as Noise Generators Using NoC Platform for Hardware Security Applications Ngo,  ... 
doi:10.1109/socc46988.2019.9088078 fatcat:wzmgb42mjzbu5hvgccttlhw3zu

Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project

R Ammendola, A Biagioni, P Cretaro, O Frezza, F Lo Cicero, A Lonardo, M Martinelli, P S Paolucci, E Pastorelli, F Pisani, F Simula, P Vicini (+5 others)
2017 Journal of Physics, Conference Series  
The adoption of low-cost, Linux-based clusters extended the reach of HPC from its roots in modelling and simulation of complex physical systems to a broader range of industries, from biotechnology, cloud  ...  These challenges lie as stumbling blocks along the road towards Exascale-class systems; the ExaNeSt project acknowledges them and tasks itself with investigating ways around them.  ...  On the other hand, a global physical address points to a fixed physical location.  ... 
doi:10.1088/1742-6596/898/8/082045 fatcat:7tytbz7ao5gwxh6oxoxrxcrmxm

VPR 5.0

Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Jonathan Rose
2009 Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '09  
To illustrate the use of the new features, we present a new look at the FPGA area vs. logic block LUT size question that shows that small LUT sizes, with the use of carefully optimized electrical design  ...  in the majority of FPGAs sold, and which have signficantly different architectural and electrical properties from the multi-driver approach previously modelled.  ...  the implementation used in VPR 5.0.  ... 
doi:10.1145/1508128.1508150 dblp:conf/fpga/LuuKJCYFR09 fatcat:iijl7js7xjdsvaqroveon6epte
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