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Roughness of microarchitectural design topologies and its implications for optimization

Benjamin C. Lee, David Brooks
2008 High-Performance Computer Architecture  
Thus, this work quantifies the implications of design topology roughness for commonly used methods and practices in microarchitectural analysis.  ...  To most effectively utilize these now computationally tractable techniques, we characterize design topology roughness and leverage this characterization to guide our usage of analysis and optimization  ...  Any opinions, findings, conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation, Intel, or IBM.  ... 
doi:10.1109/hpca.2008.4658643 dblp:conf/hpca/LeeB08 fatcat:6qk4kdluzfhdnkqnnlfip3p3fe

Designing Chip-Level Nanophotonic Interconnection Networks

Christopher Batten, Ajay Joshi, Vladimir Stojanovic, Krste Asanovic
2012 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
This paper discusses the approach we have used when designing such networks, and provides a foundation for designing new networks.  ...  We begin by briefly reviewing the basic silicon-photonic device technology before outlining design issues and surveying previous nanophotonic network proposals at the architectural level, the microarchitectural  ...  ACKNOWLEDGMENT The authors would like to thank our co-authors on the various publications that served as the basis for the three case studies, including Y.  ... 
doi:10.1109/jetcas.2012.2193932 fatcat:v6marconr5cabl5ipnnxeyxsmu

Designing Chip-Level Nanophotonic Interconnection Networks [chapter]

Christopher Batten, Ajay Joshi, Vladimir Stojanovć, Krste Asanović
2012 Integrated Optical Interconnect Architectures for Embedded Systems  
This chapter discusses the approach we have used when designing such networks, and provides a foundation for designing new networks.  ...  We then outline design issues and categorize previous proposals in the literature at the architectural level, the microarchitectural level, and the physical level.  ...  We would like to thank our co-authors on the various publications that served as the basis for the three case studies, including Y.  ... 
doi:10.1007/978-1-4419-6193-8_3 fatcat:rqyqnccg4nhx5lwiabju5d3dwa

Exact and approximate algorithms for the extension of embedded processor instruction sets

L. Pozzi, K. Atasu, P. Ienne
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In embedded computing, cost, power, and performance constraints call for the design of specialized processors, rather than for the use of the existing off-the-shelf solutions.  ...  It proposes exact algorithms to derive optimal ISEs; exact identification of a single ISE is applicable to basic blocks of up to 1500 assembler-like instructions.  ...  Fig. 13 . 13 Three examples of basic blocks with different implications on the optimality of the pseudooptimal selection algorithm.  ... 
doi:10.1109/tcad.2005.855950 fatcat:3ndayy3bbbbunas65soa5jrpku

Architectural bone parameters and the relationship to titanium lattice design for powder bed fusion additive manufacturing [article]

Martine McGregor, Sagar Patel, Stewart McLachlin, Mihaela Vlasea
2021 arXiv   pre-print
Ti and Ti-6Al-4V have favourable biocompatibility, corrosion resistance and fatigue strength for bone applications; yet, the optimal parameters for Ti-6Al-4V lattice designs corresponding to the natural  ...  This review contributes to the body of knowledge by identifying the correspondence of Ti and Ti-6Al-4V lattices to the natural parameters of bone microarchitectures, and provides further guidance on the  ...  There is still no consensus on optimal surface topology and roughness for osseointegration and adhesion, as changes in the microstructure and nanostructure of lattice surfaces both influence the cell response  ... 
arXiv:2105.07945v2 fatcat:wolbsqfcgffhbatqfqw7jcrg4i

Silver nanoprisms/graphene oxide/silicon nanowires composites for R6G surface-enhanced Raman spectroscopy sensor

2020 Biointerface Research in Applied Chemistry  
In this study, Silver nanoprisms/Graphene Oxide/Silicon nanowires (AgNPr/GO/SiNWs) nanocomposites have been fabricated for Surface-Enhanced Raman Spectroscopy (SERS) of Rhodamine 6G (R6G).  ...  The surface morphologies of the SiNWs samples have been investigated using scanning electron microscopy.  ...  We attempted to study the implications of etching time on silicon nanowires topology and SERS response by integrating with AgNPr and GO.  ... 
doi:10.33263/briac103.670674 fatcat:uxel3kuugbgatoo6vrzvt4stja

Towards layout-friendly high-level synthesis

Jason Cong, Bin Liu, Guojie Luo, Raghu Prabhakar
2012 Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design - ISPD '12  
Experimental results have demonstrated correlations between the metrics and the routability of the resulting design.  ...  There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability.  ...  Guojie Luo would like to thank the Center for Energy-Efficient Computing and Applications at Peking University for providing start-up research fund.  ... 
doi:10.1145/2160916.2160952 dblp:conf/ispd/CongLLP12 fatcat:becgfn67cbggppc5a2gewbw4jy

Scalability of Broadcast Performance in Wireless Network-on-Chip

Sergi Abadal, Albert Mestres, Mario Nemirovsky, Heekwan Lee, Antonio Gonzalez, Eduard Alarcon, Albert Cabellos-Aparicio
2016 IEEE Transactions on Parallel and Distributed Systems  
Such design is conceived to provide low latency and ordered delivery for multicast/broadcast traffic, in an attempt to complement a wireline NoC that will transport the rest of communication flows.  ...  Based on this evaluation, preliminary results on the potential performance of the proposed hybrid scheme are provided, together with guidelines for the design of MAC protocols for WNoC.  ...  This work has been also partially supported by the Catalan Government through a FI-AGAUR grant and by the Spanish State Ministry of Economy and Competitiveness under grant aid PCIN-2015-012.  ... 
doi:10.1109/tpds.2016.2537332 fatcat:n7vqmnthpvdcrjndtnlka5rfh4

PerfSim: A Performance Simulator for Cloud Native Computing [article]

Michel Gokan Khan, Javid Taheri, Auday Al-Dulaimy, Andreas Kassler
2021 arXiv   pre-print
For understanding and analyzing these implications in an easy, quick, and cost-effective way, we present PerfSim, a discrete-event simulator for approximating and predicting the performance of cloud native  ...  With a combination of the extracted models and user-defined scenarios, PerfSim can simulate the performance behavior of service chains over a given period and provides an approximation for system KPIs,  ...  Simulating large scale service chains When designing PerfSim, we initially aimed to use it for optimizing large-scale service chains.  ... 
arXiv:2103.08983v1 fatcat:dfaunpe755eedlgl3wp4ekkhna

Microarchitecture-dependent nonlinear bending analysis for cellular plates with prismatic corrugated cores via an anisotropic strain gradient plate theory of first-order shear deformation

Jalal Torabi, Jarkko Niiranen
2021 Engineering structures  
shear deformation This study focuses on the microarchitecture-dependent nonlinear bending behavior of cellular plates with equitriangularly prismatic microarchitectures by adopting a dimensionally and  ...  Torabi, Jalal; Niiranen, Jarkko Microarchitecture-dependent nonlinear bending analysis for cellular plates with prismatic corrugated cores via an anisotropic strain gradient plate theory of first-order  ...  Based on different design aspects such as shape, size and topology, cellular structures with different microarchitectures can be extensively used in a variety of industrial applications such as lightweight  ... 
doi:10.1016/j.engstruct.2021.112117 fatcat:7inwhg3jefbmba3y2vexef2mtm

Transverse loading of cellular topologically interlocked materials

S. Khandelwal, T. Siegmund, R.J. Cipra, J.S. Bolton
2012 International Journal of Solids and Structures  
The implications of the present findings for the design of these novel materials are discussed.  ...  Topologically interlocked materials (TIMs) are a class of materials made by a structured assembly of an array of identically shaped and sized unit elements that are held in a confining framework.  ...  Acknowledgements The authors gratefully acknowledge the support provided for this research by the AFOSR, Program Manager, Dr. Les Lee via Grant# FQ8671-090162.  ... 
doi:10.1016/j.ijsolstr.2012.04.035 fatcat:3w6ttxez3vhddbn5nfolgfj6wu

Cellular activities of osteoblast-like cells on alkali-treated titanium surface

Jin-Woo Park, Deog-Hye Lee, Shin-Il Yeo, Kwang-Bum Park, Seok-Kyu Choi, Jo-Young Suh
2007 The Journal of the Korean Academy of Periodontology  
Such surface modifications can be divided into two classes, one aiming on optimized three-dimensional physical microarchitecture of the surface, and the other focusing on the biochemical properties of  ...  Also we could not observe the synergistic effect by TiO 2 layer composed of anatase, although it is not clear as the design of this study.  ... 
doi:10.5051/jkape.2007.37.suppl.427 fatcat:gzh276o6rvggjgnyoox7gkaef4

Low power network on chip architectures: A survey

Muhammad Raza Naqvi
2020 Computer Science and Information Technologies  
nodes, network design, and routers.  ...  This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between  ...  Main functioning in network transmission is buffering, and its size optimization has become a good research task for scholars.  ... 
doi:10.11591/csit.v2i3.p158-168 fatcat:rzmirvcyxfao7pu3k2nxsjmhzy

An intra-chip free-space optical interconnect

Jing Xue, Michael Huang, Hui Wu, Eby Friedman, Gary Wicks, Duncan Moore, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain (+2 others)
2010 Proceedings of the 37th annual international symposium on Computer architecture - ISCA '10  
The interconnect avoids packet relay altogether, offers an ultra-low transmission latency and scalable bandwidth, and provides fresh opportunities for coherency substrate designs and optimizations.  ...  ; Section 4 and 5 discuss the architectural design issues and optimizations; Section 6 presents the quantitative analysis; Section 7 discusses related work; and Section 8 concludes.  ...  For a rough sense of scale, for N = 16, k = 9 (our default configuration for evaluation), we need approximately 2000 VCSELs. Existing VCSELs are about 20µmx20µm in dimension [16, 17] .  ... 
doi:10.1145/1815961.1815975 dblp:conf/isca/XueGCHWSJBLHWFWM10 fatcat:6v33dyjvrbfnbowt3xetdxpuvy

An intra-chip free-space optical interconnect

Jing Xue, Michael Huang, Hui Wu, Eby Friedman, Gary Wicks, Duncan Moore, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain (+2 others)
2010 SIGARCH Computer Architecture News  
The interconnect avoids packet relay altogether, offers an ultra-low transmission latency and scalable bandwidth, and provides fresh opportunities for coherency substrate designs and optimizations.  ...  ; Section 4 and 5 discuss the architectural design issues and optimizations; Section 6 presents the quantitative analysis; Section 7 discusses related work; and Section 8 concludes.  ...  For a rough sense of scale, for N = 16, k = 9 (our default configuration for evaluation), we need approximately 2000 VCSELs. Existing VCSELs are about 20µmx20µm in dimension [16, 17] .  ... 
doi:10.1145/1816038.1815975 fatcat:grlihetgpbarlifjxaq22xpmuy
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