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Robust activating timing for SRAM SA with replica cell voltage boosted circuit
2016
IEICE Electronics Express
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A boosted replica cell voltage control scheme has been proposed for reducing the process-variation of SRAM sense amplifier. ...
This technique suppresses the timing variation by boosting the replica cell voltage. ...
Conclusions In order to reduce the timing variation of SRAM sense amplifier signal, a boosted replica cell voltage control scheme has been proposed. ...
doi:10.1587/elex.13.20160302
fatcat:y4brsabqmvbyjjlsnm4ufgox54
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
2012
IEEE Journal of Solid-State Circuits
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Index Terms-Low power, low voltage, negative bit-line (BL), subthreshold SRAM cell, timing tracing. ...
The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology ...
His research interests include noise suppression design technologies, embedded measurement circuit design, and ultra-low-power SRAM design.
Jihi-Yu ...
doi:10.1109/jssc.2012.2187474
fatcat:acydfavabfebdjgozk5bwawujm
TS Cache: A Fast Cache with Timing-speculation Mechanism Under Low Supply Voltages
[article]
2019
arXiv
pre-print
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This paper proposes the Timing-Speculation (TS) cache to boost the cache frequency and improve energy efficiency under low supply voltages. ...
However, the read delay distribution of the SRAM cells under the near-threshold voltage shows a more serious long-tail characteristic than that under the nominal voltage due to the process fluctuation. ...
Circuit-level Solutions Regarding circuit-level solutions for the low-power SRAM, larger transistors in a memory cell average out the Vth variability caused by non-uniformities in the channel doping and ...
arXiv:1904.11200v1
fatcat:lyugtzzjtjaz5kf5ywdgxljkn4
10T SRAM Computing-in-Memory Macros for Binary and Multibit MAC Operation of DNN Edge Processors
2021
IEEE Access
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Fig. 11 shows the schematic of the SA. The SA is based on a Strong-Arm latch comparator and the input boosting circuit (IBC). ...
The SA cell compares this analog voltage with V REF to produce a binary output.
FIGURE 4 . 4 Overall architecture of the proposed SRAM-CIM for binary MAC operation. FIGURE 5. ...
doi:10.1109/access.2021.3079425
fatcat:oftur4nhh5hhvkrf6kgezptfyy
Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C
2014
IEEE Journal of Solid-State Circuits
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It consists of two replica bitlines with hardwired data patterns (one for reading data '0' and the other for reading data '1'), sense amplifiers (SAs), two counters, V ref ladders, I ref generating devices ...
To tackle this issue, we propose circuit techniques facilitating both enhanced bitline swing and a widened sensing timing window. for data '1' occurs with I lkg-max while that for data '0' with I lkg-min ...
doi:10.1109/jssc.2014.2338860
fatcat:l6a7couxufetrbpsecpxixufua
Review and classification of gain cell eDRAM implementations
2012
2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel
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With the increasing requirement of a high-density, high-performance, low-power alternative to traditional SRAM, Gain Cell (GC) embedded DRAMs have gained a renewed interest in recent years. ...
Several industrial and academic publications have presented GC memory implementations for various target applications, including high-performance processor caches, wireless communication memories, and ...
The traditional choice of embedded memories has been the 6T SRAM, as it provides high-speed read and write performance with robust static data retention. ...
doi:10.1109/eeei.2012.6377022
fatcat:wrf43obipzeklny4fpnmg5bvky
Quasi-Schottky-Barrier UTBB SOI MOSFET for Low-Power Robust SRAMs
2017
IEEE Transactions on Electron Devices
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The simulation results show a leakage reduction of 18% at V DD = 1 V in comparison with the 6T-SRAM cell realized by conventional symmetric UTBB SOI device. ...
INTRODUCTION S CALING CMOS technology facilitates digital circuits with higher speed, lower power consumption, and area efficiency. ...
In circuit and architecture level, techniques such as negative bitline (BL) [13] , boosted wordline (WL) [15] , and transient voltage collapse write assist [16] can be applied to the 6T-SRAM cell to ...
doi:10.1109/ted.2017.2672968
fatcat:xw7fxwsainc4floobzfi7cq5t4
High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs
2016
2016 International Conference on Field-Programmable Technology (FPT)
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In this work, we conduct a detailed comparison study of SRAM and MTJ BRAMs that includes cell designs that are robust with device variation, transistor-level design and optimization of all the required ...
BRAM-specific circuits, and variation-aware simulation at the 22nm node. ...
ACKNOWLEDGMENT The authors would like to thank Andrew Putnam and David Lewis for helpful discussions, and the Connaught Scholarship, Toshiba, Altera, and NSERC for funding support. ...
doi:10.1109/fpt.2016.7929181
dblp:conf/fpt/TatsumuraYB16
fatcat:5rzth546zjcefidkbcghb3yuxe
Low Power Design for Future Wearable and Implantable Devices
2016
Journal of Low Power Electronics and Applications
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This can be dealt with by further researching cooling and packaging in order to avoid overheating the circuits; however, this is an expensive and time limited solution, so this paper addresses methods ...
supply voltage utilizing low-voltage design techniques. ...
Access time is defined as the time required for discharging the bit-line to a sensible voltage for the SA after asserting the RWL. ...
doi:10.3390/jlpea6040020
fatcat:tf7shjsb25ckjmobfshjrxyqmm
Novel Approaches Toward Area- and Energy-Efficient Embedded Memories
2014
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of power management and SRAM. ...
I am also grateful to Anatoli Mordakhay who devised and measured several gain-cell test circuits. ...
Replica Technique for Auto-Refresh Timing Retention Time of a 2T Gain Cell In order to demonstrate the replica technique for optimum refresh timing, we consider the same all-PMOS 2T GC topology as for ...
doi:10.5075/epfl-thesis-6074
fatcat:4q3q7qy6p5f7nakakhkwyqmi2y
Conceptual design and multidisciplinary optimization of in-plane morphing wing structures
2006
Smart Structures and Materials 2006: Modeling, Signal Processing, and Control
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Using the experimental system, 2Hz mono-frequency is used for excitation of ER damper and the damping force is measured by load-cell. ...
Compared with an equivalent single layer theory, the prediction is more accurate for all degrees of freedom especially for thick plates. ...
With most of the switching logics, electric current flows in the circuit only for a short time, and the circuit is open for most of the time. ...
doi:10.1117/12.658686
fatcat:rqnvt2atkjgnvpog5pivwjejzm
Welcome Messages
2019
2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)
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The database along with its source code will be made open source for the research and academic purpose. ...
With the spread of mobile devices, image and video transmission is in great demand. ...
The replica TIA simply produces a DC voltage that tracks the dark level of the voltage over process, voltage and temperature. ...
doi:10.1109/ispacs48206.2019.8986291
fatcat:gu4zaxsqkncp5n2ebj5fybk7ce
SRAM Reliability Improvement Using ECC and Circuit Techniques
2018
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While most study has focused on the static random access memory (SRAM) cell array, for high-reliability products, it is important to examine the effects of failures on the peripheral logic as well. ...
In this thesis we examine the landscape of design techniques for reliability, and introduce two novel contributions for improving reliability with low overhead. ...
to cells active during a read, and similarly for the write bias assist. ...
doi:10.1184/r1/6723140.v1
fatcat:gdfwa553yfdjhgnt7pbfk5yew4
Performance Variation in Digital Systems:Workload Dependent Modeling and Mitigation
[article]
2021
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Again, we will study the robustness of the SRAM cell during the hold operation, represented by the SNM metric. ...
a memory cell, especially for large SRAM blocks. ...
The ratio of the dice that are working correctly, to the total number of dice
A.2 CDW Approximation The computational overhead for a dynamic timing simulation of a circuit design is directly coupled ...
doi:10.26240/heal.ntua.21941
fatcat:6i5vt2rk3jaabdxtublpupx43y
Design and Optimization for Resilient Energy Efficient Computing
2019
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At circuit-level, robust standard cell libraries [28] , memories [167, [169] [170] [171] and flip-flops [60, 74] are optimized for NTC. ...
Representative
Workloads
Gate-level
Simulation
Power
Estimation
Voltage Drop
Estimation
Signal Probability (SP),
Switching Activity (SA) of
all nets
Voltage Drop
-critical
Flop-Flops ...
doi:10.5445/ir/1000093975
fatcat:bktzmml4vrd5bl6aufhfdnwf6i
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