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Robust media processing in a flexible and cost-effective network of multi-tasking coprocessors

M.J. Rutten, J.T.J. van Eijndhoven, E.-J.D. Pol
Proceedings 14th Euromicro Conference on Real-Time Systems. Euromicro RTS 2002  
Each coprocessor is multi-tasking, allowing multiple applications to proceed concurrently.  ...  The scalable architecture template supports multiple function-specific coprocessors that operate in parallel and independently.  ...  Robust resource-sharing Support for multi-tasking is essential in achieving flexibility of the architecture towards configuring a range of applications and reapplying the same hardware coprocessors at  ... 
doi:10.1109/emrts.2002.1019202 dblp:conf/ecrts/RuttenEP02 fatcat:url2hs4labb6dhgaiaoh7esau4

MC-Sim: An efficient simulation tool for MPSoC designs

Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman
2008 2008 IEEE/ACM International Conference on Computer-Aided Design  
In this paper, we present MC-Sim, a heterogeneous multi-core simulator framework which is capable of accurately simulating a variety of processor, memory, NoC configurations and application specific coprocessors  ...  We have used this framework to simulate a number of real-life applications such as the MPEG4 decoder and litho-simulation, and experimented with a number of design choices.  ...  ACKNOWLEDGEMENTS This work is partially supported by the MARCO GSRC center, the SRC contract 2005-TJ-1317, and the NSF grant CNS-0725354.  ... 
doi:10.1109/iccad.2008.4681599 dblp:conf/iccad/CongGHKNR08 fatcat:lrhz75drcbf6zgntmrac6qtt2y

In-vehicle vision processors for driver assistance systems

Shorin Kyo, Shin'ichiro Okazaki
2008 2008 Asia and South Pacific Design Automation Conference  
Relationship between performance, cost, and flexibility, and the Control versus Operational circuit Ratio (COR). (a) Relationship between performance, cost, and flexibility.  ...  Then several in-vehicle vision processor LSI implementations are reviewed, and the design approach of one of them, the IMAPCAR highly parallel processor, is further described in detail.  ...  Kuroda of NEC Electronics Corporation, and Dr. Nishiwaki and Mr. Takahashi of NEC Corporation for their valuable inputs.  ... 
doi:10.1109/aspdac.2008.4483980 dblp:conf/aspdac/KyoO08 fatcat:5r3wau43nfhxhjqeht4nwwv3a4

Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications

Francisco Fons, Mariano Fons, Enrique Cantó, Mariano López
2011 Journal of Real-Time Image Processing  
In our pioneer conception, these tasks are partitioned and synthesized first in a series of coprocessors that are then instantiated and executed multiplexed in time on a partially reconfigurable region  ...  Biometric personal recognition is a good example of compute-intensive algorithm composed of a series of image processing tasks executed in a sequential order.  ...  the source code of an application is written and processed in parallel through multi-threading.  ... 
doi:10.1007/s11554-010-0186-1 fatcat:j5by7g5vpbfv3egkmqd6mzwhnq

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures

C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara (+17 others)
2010 2010 IEEE Computer Society Annual Symposium on VLSI  
The main goals of the 2PARMA project are: the definition of a parallel programming model combining component-based and singleinstruction multiple-thread approaches, instruction set virtualisation based  ...  The 2PARMA project focuses on the development of parallel programming models and run-time resource management techniques to exploit the features of many-core processor architectures.  ...  In addition to dualand quad-core general-purpose processors, more scalable multi-core architectures are widely adopted for high-end graphics and media processing, e.g.  ... 
doi:10.1109/isvlsi.2010.93 dblp:conf/isvlsi/SilvanoFCAPZBCCBSTSHSBPRYBXSKALMAMV10 fatcat:6slhzv6pnnclzlgfydqiafrzxm

2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures [chapter]

C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara (+19 others)
2011 Lecture Notes in Electrical Engineering  
The main goals of the 2PARMA project are: the definition of a parallel programming model combining component-based and singleinstruction multiple-thread approaches, instruction set virtualisation based  ...  The 2PARMA project focuses on the development of parallel programming models and run-time resource management techniques to exploit the features of many-core processor architectures.  ...  In addition to dualand quad-core general-purpose processors, more scalable multi-core architectures are widely adopted for high-end graphics and media processing, e.g.  ... 
doi:10.1007/978-94-007-1488-5_5 fatcat:eziaamxixfcu3cvqbqivetedu4

Resource Reservations in Shared-Memory Multiprocessor SoCs [chapter]

Clara Otero Pérez, Martijn Rutten, Liesbeth Steffens, Jos van Eijndhoven, Paul Stravers
2005 Philips Research  
The presented virtual platform approach aims to integrate the reservation mechanisms of each shared SoC resource as the first step towards robust, yet flexible and cost-effective consumer products.  ...  With the convergence of storage, digital television, and connectivity, these media-processing systems must support numerous operational modes.  ...  ACKNOWLEDGEMENT The authors want to express their gratitude to Peter van der Stok, and Kees Goosens for their review comments.  ... 
doi:10.1007/1-4020-3454-7_5 fatcat:jjrlt3m62nfujegqgi32qj4p4u

Energy-Efficient System-Level Design [chapter]

Luca Benini, Giovanni De Micheli
2002 Power Aware Design Methodologies  
and communication channel as well as system and application software onto a single chip.  ...  The complexity of current and future integrated systems requires a paradigm shift towards component-based design techno logies that enable the integration of large computational cores, memory hierarchies  ...  The sizing and synthesis of embedded storage arrays poses new challenges, because the effectiveness of multi-processing is often limited by the ability to transfer and store information.  ... 
doi:10.1007/0-306-48139-1_16 fatcat:rikxlmoqmjfd3o3whfmbnvymwm

Broadcast and Weight: An Integrated Network For Scalable Photonic Spike Processing

Alexander N. Tait, Mitchell A. Nahmias, Bhavin J. Shastri, Paul R. Prucnal
2014 Journal of Lightwave Technology  
Broadcast-and-weight is a new approach for combining neuromorphic processing and optoelectronic physics, a pairing that is found to yield a variety of advantageous features.  ...  Designs for a network protocol, computational element, and waveguide medium are described, and novel methods are considered in relation to prior research in optical on-chip networking, neural networking  ...  On the other hand, the effect of noise on pulse timing (i.e., jitter) is relevant in determining spike precision and channel capacity. 2) Robustness: Suppose a given distributed processing task requires  ... 
doi:10.1109/jlt.2014.2345652 fatcat:4mwhpxwj4ra3bow77rxxqr4wve

Reconfigurable Hardware Accelerators: Opportunities, Trends, and Challenges [article]

Chao Wang, Wenqi Lou, Lei Gong, Lihui Jin, Luchao Tan, Yahui Hu, Xi Li, Xuehai Zhou
2017 arXiv   pre-print
In the end, we prospect the development tendency of accelerator architectures in the future, hoping to provide a reference for computer architecture researchers.  ...  Nowadays, in top-tier conferences of computer architecture, emerging a batch of accelerating works based on FPGA or other reconfigurable architectures.  ...  The Zynq-7000 [10] , a programmable heterogeneous multi-core system-on-chip introduced by Xilinx Inc., consists of programmable logic devices and processing systems and features configurability, flexibility  ... 
arXiv:1712.04771v1 fatcat:3lxv45qb4zaqpagtn3eghrmroe

The AURORA gigabit testbed

David D. Clark, Bruce S. Davie, David J. Farber, Inder S. Gopal, Bharath K. Kadaba, W. David Sincoskie, Jonathan M. Smith, David L. Tennenhouse
1993 Computer networks and ISDN systems  
Each approach has its advantages, and they will coexist in the national network of tomorrow.  ...  Conversion between ATM cells and variable length packets is handled in a host interface, described in Section 4.2  ...  Obvious examples of application requirements for service integration are multi-media information transfer (in support of live video conferencing) or the storage and retrieval of multi-media documents.  ... 
doi:10.1016/0169-7552(93)90056-a fatcat:6mc6vxelhnhphc4nsnkliejany

OS Support for Load Scheduling on Accelerator-based Heterogeneous Systems

Ayman Tarakji, Niels Ole Salscheider, David Hebbeker
2014 Procedia Computer Science  
The involvement of accelerators is becoming widespread in the field of heterogeneous processing, performing computation tasks through a wide range of applications.  ...  Besides the different CPUs, a variety of modern GPU and other accelerator architectures are used in the experiments.  ...  In the sense of sharing the coprocessor efficiently, our scheduler pursues a higher utilization of processing resources inherently, manages the operative parts of the coprocessor, and improves the task  ... 
doi:10.1016/j.procs.2014.05.021 fatcat:w6myygnte5g2zjefkrakyfvefy

System Level Distributed Cooperative Design of Media SoC Using Application Profiling

Dawei Wang, Peng Zhao, Sikun Li
2009 Journal of Computers  
Experimental results show that the method effectively improves the quality and speed of media SoC design.  ...  This paper presents a collaborative approach of media SoC design using application profiling.  ...  ACKNOWLEDGMENT This work is sponsored by the National Science Foundation of China under the grant NO.90207019 and NO.90707003.  ... 
doi:10.4304/jcp.4.1.77-85 fatcat:o3q6zai6ujg65ljj7kcjtghm3a

Embedded Intelligence: State-of-the-Art and Research Challenges

Kah Phooi Seng, Li-Minn Ang
2022 IEEE Access  
This paper presents a comprehensive survey on EI from four aspects: (1) First, the state-of-the-art for EI using a set of evaluation criteria is proposed and reviewed; (2) Second, EI for both cloud server  ...  4) The paper concludes with the lessons learned and the future prospects are discussed in terms of the key role EI is likely to play in emerging technologies and applications such as Industry 4.0.  ...  She was a Professor and the Department Head of computer science and networked system with Sunway University.  ... 
doi:10.1109/access.2022.3175574 fatcat:7hcwlhg5njcfzf5zym25oxhqbe

Methods for evaluating and covering the design space during early design development

M GRIES
2004 Integration  
It is focused on System-on-a-Chip designs, particularly those used for network processors.  ...  This review thus eases the choice of a decent exploration policy by providing a comprehensive survey and classification of recent related work.  ...  This work was supported, in part, by the Microelectronics Advanced Research Consortium (MARCO) and Infineon Technologies, and is part of the efforts of the Gigascale Silicon Research Center (GSRC).  ... 
doi:10.1016/s0167-9260(04)00032-x fatcat:j7mgqssclnehrbszo7ktv64edq
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