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SRAM Cells for Embedded Systems [chapter]

Jawar Singh, Balwinder Raj
2012 Embedded Systems - Theory and Design Methodology  
Through our work, we have tried to bridge these technical gaps in order to have better novel cells for low power applications in future embedded SRAM.  ...  Articles on implementation of novel devices such as FinFET and Tunnel diode based 6T-SRAM cell for embedded system, which is having low leakage, high SNM and high speed were also incorporated.  ...  SRAM Cells for Embedded Systems, Embedded Systems -Theory and Design Methodology, Dr.  ... 
doi:10.5772/37094 fatcat:scoh544npfhwxpvxliekjunrpe

Simpler, more efficient design

Borivoje Nikolic
2015 ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)  
Open-source repository of function generators and their mappings into systems allow designers to selectively add value to the design.  ...  Function generators, as opposed to function instances, should be designed, which combined with higher-level design abstraction improve design efficiency and foster reuse.  ...  Many of author's colleagues and current and former students have contributed to the ideas presented in this paper, including, Krste Asanovic, Jonathan Bachrach, Elad Alon, Robert Brodersen, Dejan Markovic  ... 
doi:10.1109/esscirc.2015.7313819 dblp:conf/esscirc/Nikolic15 fatcat:tqsxgusdjzc5tbws2deheswziy

Design Principles of SRAM Memory in Nano-CMOS Technologies

Ezeogu Chinonso
2019 International Journal of Computer Applications  
Static Random Access Memory (SRAM) is a volatile memory that is widely used in every embedded system -Silicon on Chip (SoC), Digital Signal Processing (DSP), Microcontroller, Field Programmable Gate Array  ...  It is also used in register, cache and cache-less applications due to large storage *density, reduced read-write access time, low power consumption and stability.  ...  INTRODUCTION SRAM memory is still currently the main memory block of today's embedded systems and computing devices cache and register designs.  ... 
doi:10.5120/ijca2019918395 fatcat:k55l4fdnfvhu7maowm3sbklc5a

Design of 3T Gain Cell for Ultra Low Power Applications

V Lavanya
2017 International Journal for Research in Applied Science and Engineering Technology  
Design of a power efficient SRAM cell is one of the most important factor in order to achieve better chip performance. This paper presents a stable SRAM Gain Cell for low power applications.  ...  The 6T SRAM has been the traditional choice for the implementation of embedded memories due to its high-access speed and refresh-free static data retention.  ...  Readout circuitry Many previous low-voltage embedded memories, targeted at ULP systems, employ a simple sense inverter in order to provide robust, low-area, and low-power data readout.  ... 
doi:10.22214/ijraset.2017.11309 fatcat:rzfryv46erb2fk2zsdllamxj5m

DESIGN AND READ STABILITYANALYSIS OF 8T SCHMITT TRIGGER BASED SRAM

Priyanka Lee Achankunju, Sreekala K S, Marie K. James
2017 ICTACT Journal on Microelectronics  
This paper presents an 8T Schmitt Trigger (ST) based SRAM design to improve the read stability and power dissipation of conventional 6T SRAM cell.  ...  The ST based SRAM cell incorporates built-in feedback mechanism in order to attain robust read operation.  ...  During the last decade, low power and robust memory designs have drawn great research attention.  ... 
doi:10.21917/ijme.2017.0056 fatcat:qvbu5fcmmfhpbbt4zspp6bhgse

Design and implementation of Dual-Port Memory

Chandrashekar C, Department of Electronics and Communication B.N.M. Institute of Technology, Bangalore, India., Dr.Basavaraj I Neelgar, Department of Electronics and Communication B.N.M. Institute of Technology, Bangalore, India.
2021 Journal of University of Shanghai for Science and Technology  
Multiport memory cell using a dual-port memory cell provides required access to multi-processor-based applications.  ...  Using specific word lines and bit lines of SRAM cell access can be provided by using dual ports memory.  ...  INTRODUCTION SRAM memories are the primary element of System-On-Chip (SOC). SRAM systems suffer from the disadvantage that they occupy more area which affects power and the yield.  ... 
doi:10.51201/jusst/21/06478 fatcat:3jjidw3k4bh37jhssh6dpa6af4

Process Variations and Process-Tolerant Design

Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
2007 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)  
and memory.  ...  Variations in the device parameters, both systematic and random, translate into variations in circuit parameters like delay and leakage power, leading to loss in parametric yield.  ...  Robustness with respect to variations and low power operations typically impose contradictory design requirements.  ... 
doi:10.1109/vlsid.2007.131 dblp:conf/vlsid/BhuniaMR07 fatcat:haw2cidqhng7ngucgvwiftnsza

Recent Subthreshold Design Techniques

Mohsen Radfar, Kriyang Shah, Jugdutt Singh
2012 Active and Passive Electronic Components  
Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications.  ...  Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development  ...  for subthreshold operations and, to maximise the robustness, some cells were eliminated from it).  ... 
doi:10.1155/2012/926753 fatcat:tjiwpmwmbnd7hj3m73vh4dhtl4

DECOUPLING LOGIC BASED SRAM DESIGN FOR POWER REDUCTION IN FUTURE MEMORIES

M. PREMKUMAR, CH. JAYA PRAKASH
2014 International Journal of Electronics Signals and Systems  
In this paper we are going to modify the column decoupled SRAM for the purpose of more reduced leakages than the existing type of designs as well as the new design which is combined of virtual grounding  ...  with column decoupling logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors the simulations were  ...  Different SRAM designs have previously been presented that use from 6 to 10 transistors to provide reliable and/or low power operation.  ... 
doi:10.47893/ijess.2014.1207 fatcat:5yxjioghvje4to2ssfgr4x26by

Secured Hardware Design - An Overview

Sasikiran Burugapalli, Waleed K. Al-Assadi
2008 2008 IEEE Region 5 Conference  
Security is a prime concern in the design of a wide variety of embedded systems and security processors.  ...  Due to the design time issues weakness in the design is often revealed in the manufactured chips.  ...  For example consider an SRAM memory cell as shown in fig. 2 . When the word line is low, the data will be stored in the cell using the inverters which are connected back-back.  ... 
doi:10.1109/tpsd.2008.4562750 fatcat:gxuq7z7osvctvh563lwzsdvsqm

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

Mahmut E. Sinangil, Marcus Yip, Masood Qazi, Rahul Rithe, Joyce Kwong, Anantha P. Chandrakasan
2012 IEEE Transactions on Circuits and Systems - II - Express Briefs  
This paper covers the main building blocks of a system implementation including digital logic, embedded memories and analog-to-digital conversion and describes the challenges and solutions to designing  ...  Increasing number of energy-limited applications continue to drive the demand for designing systems with high energy efficiency.  ...  Alternative Low-Power Embedded Memories Recent work at nominal voltages has replaced embedded SRAM with DRAM to reduce cost [40] .  ... 
doi:10.1109/tcsii.2012.2208675 fatcat:b25ubotnpvd3tkhrzbhuwe4s4i

A low power 256 KB SRAM design

B. Bhaumik, P. Pradhan, G.S. Visweswaran, R. Varambally, A. Hardi
1999 Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)  
In this paper a low power SRAM design is presented. Existing SRAM architectures used in SGSThomson were studied to explore the possibilities in bringing down power dissipation in various blocks.  ...  Particular emphasis was put to reduce power consumption in decoders. A new critical path model was introduced for schematic simulation. This lowered the simulation time considerably.  ...  Consequently low power SRAM design has become an increasingly important aspect in design [1] .  ... 
doi:10.1109/icvd.1999.745126 dblp:conf/vlsid/BhaumikPVVH99 fatcat:2wunke44dvb5vmg3lgwowqjvby

Hybrid-cell register files design for improving NBTI reliability

N. Gong, S. Jiang, J. Wang, B. Aravamudhan, K. Sekar, R. Sridhar
2012 Microelectronics and reliability  
In this paper, a hybrid-cell RF design technique is proposed to achieve high reliability by storing the most vulnerable bits in robust 8T cells and other bits in conventional 6T cells.  ...  Simulation results in 32 nm predicative CMOS process show that the proposed technique achieves 11.4% and 24.8% RF reliability improvement in high performance system and embedded system, respectively, while  ...  Proposed robust RF design with hybrid cells Based on the bit-aware degradation characteristics in RF and reliability of different memory cells, we proposed a hybrid-cell RF design to mitigate the NBTI  ... 
doi:10.1016/j.microrel.2012.06.045 fatcat:7sd5xhtnfbbbfnakc5iltrbq6y

Soft Errors in Advanced Computer Systems

R. Baumann
2005 IEEE Design & Test of Computers  
So, contrary to the popular misconception that the DRAM SER is problematicundoubtedly left over from the days when DRAM designs used planar cells-a DRAM is one of the more robust devices in terms of soft-error  ...  At the core of each system is a microprocessor or a digital signal processor with large embedded memories (usually SRAMs) interconnected with extensive peripheral logic.  ... 
doi:10.1109/mdt.2005.69 fatcat:wh7gezkk75gwnbk27yxya5pwzm

Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes

Yoonmyung Lee, Dongmin Yoon, Yejoong Kim, David Blaauw, Dennis Sylvester
2013 IPSJ Transactions on System LSI Design Methodology  
The design space and corresponding trade-offs for these three components are explored to suggest guidelines for the design of ultra-low power sensor nodes.  ...  Designing an ultra-low power sensor node requires careful consideration of the system-level energy budget. Depending on applications, various components can dominate total energy.  ...  Thus, embedded volatile memories (e.g., SRAM, eDRAM) are preferred in such systems, but they lose data once the power is gated, so at least the bitcell arrays must always stay on, consuming leakage power  ... 
doi:10.2197/ipsjtsldm.6.17 fatcat:hbbgw6xpofh6rbbpchg6pa3iwu
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