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Review of error correction for PUFs and evaluation on state-of-the-art FPGAs

Matthias Hiller, Ludwig Kürzinger, Georg Sigl
2020 Journal of Cryptographic Engineering  
In addition, we provide a wide span of new implementation results on state-of-the-art Xilinx FPGAs and set them in context to old synthesis results on legacy FPGAs.  ...  This work compares the performance of several previous designs on an algorithmic level concerning the required number of PUF response bits, helper data bits, number of clock cycles, and FPGA slices for  ...  , and the anonymous reviewers for the several rounds of detailed and constructive feedback.  ... 
doi:10.1007/s13389-020-00223-w fatcat:oh2ce3ugrvfozg4y6qkj3xhkhu

A Novel Ultra-Compact FPGA PUF: The DD-PUF

Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti
2021 Cryptography  
The circuits have been extensively tested under temperature and supply voltage variations and the results of our evaluations on both FPGA families have shown that the proposed architecture and implementation  ...  for all the most important figures of merit.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/cryptography5030023 fatcat:rhuqwaktbfaidbl35hijef22ve

Physical Unclonable Functions (PUF) for IoT Devices [article]

Abdulaziz Al-Meer, Saif Al-Kuwari
2022 arXiv   pre-print
In this survey we provide a comprehensive review of the state-of-the-art of PUF, its architectures, protocols and security for IoT.  ...  PUF is promising solution for lightweight security, where the manufacturing fluctuation process of IC is used to improve the security of IoT as it provides low complexity design and preserves secrecy.  ...  Acknowledgments This work is partially funded by the G5797 "Developing Physical-Layer Security Schemes for Internet of Things Networks" project under the NATO's Science for Peace Programme.  ... 
arXiv:2205.08587v1 fatcat:ytp7ot6pc5asbi46qxsdeewg2u

SCA secure and updatable crypto engines for FPGA SoC bitstream decryption: extended version

Florian Unterstein, Nisha Jacob, Neil Hanley, Chongyan Gu, Johann Heyszl
2020 Journal of Cryptographic Engineering  
To solve this, we propose a comprehensive concept that uses an alternative and side-channel protected cryptographic engine within the FPGA logic instead of the built-in one for the crucial task of bitstream  ...  The lack of accessible secret key storage poses a significant challenge and requires the use of a physical unclonable function (PUF) to generate a device intrinsic secret within the FPGA logic.  ...  The Golay error correction block consists of linear operations, and a single, constant time, table look-up indirectly based on the PUF response error.  ... 
doi:10.1007/s13389-020-00247-2 fatcat:xgnl4djeznckzatufxling2ywq

SCA Secure and Updatable Crypto Engines for FPGA SoC Bitstream Decryption

Florian Unterstein, Nisha Jacob, Neil Hanley, Chongyan Gu, Johann Heyszl
2019 Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop - ASHES'19  
reliability to allow minimal error correction of subsequent evaluations.  ...  To assess the suitability of the PUF architecture for our sidechannel protected boot design, a 256-bit output of the core PUF module was generated for testing prior to error correction being applied 3  ... 
doi:10.1145/3338508.3359573 dblp:conf/ccs/UntersteinJHGH19 fatcat:aodlbsudffc7jlrln3rigee2fa

A PUF design for secure FPGA-based embedded systems

Jason H. Anderson
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
Measured results on the Xilinx Virtex-5 65 nm FPGA demonstrate PUF signatures to be both unique and reliable under temperature variation.  ...  Our novel design makes use of the underlying FPGA architecture, and unlike prior published PUFs, the proposed PUF can be naturally embedded into a design's HDL, consuming very little area, and does not  ...  ACKNOWLEDGEMENTS The author thanks Xilinx for providing the Virtex-5 FPGA development boards. The author thanks Dr. Qiang Wang for his helpful comments on the manuscript.  ... 
doi:10.1109/aspdac.2010.5419927 dblp:conf/aspdac/Anderson10 fatcat:gvnrbbia3vc6rb6krxefli44xy

A Survey of Recent Results in FPGA Security and Intellectual Property Protection [chapter]

François Durvaux, Stéphanie Kerckhof, Francesco Regazzoni, François-Xavier Standaert
2013 Secure Smart Embedded Devices, Platforms and Applications  
Finally, we emphasize recent trends for improving IP security in FPGAs, including bitstream security, the use of code watermarking techniques and the exploitation of Physically Unclonable Functions (PUFs  ...  Next, we discuss security IPs in FPGAs, taking the example of symmetric encryption with the AES Rijndael, and including their performance evaluations and resistance against physical attacks.  ...  Specific features of state of the art FPGAs were also exploited for implementing masking: the larger input size of the basic block of Xilinx Virtex-5 FPGA was combined with optimization techniques for  ... 
doi:10.1007/978-1-4614-7915-4_9 fatcat:bp2upohaffe4nl5qlx3gykrncm

Techniques for Design and Implementation of Secure Reconfigurable PUFs

Mehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potkonjak
2009 ACM Transactions on Reconfigurable Technology and Systems  
We demonstrate how reconfigurability can be exploited to eliminate the stated PUF limitations. We also show how FPGA-based PUFs can be used for privacy protection.  ...  To address these limitations, we have developed a new set of techniques for FPGA-based PUF design and implementation.  ...  Error correcting codes with syndrome decoding have been proposed to correct for such errors [Gassend et al. 2002a ].  ... 
doi:10.1145/1502781.1502786 fatcat:yteu5mg5n5hzzavjk2izlii6uu

Low-Complexity Nonlinear Self-Inverse Permutation for Creating Physically Clone-Resistant Identities

Saleh Mulhem, Ayoub Mars, Wael Adi
2020 Cryptography  
The attained security levels of the resulting SUCs are evaluated and shown to be scalable and usable even for post-quantum crypto systems.  ...  Hardware and software complexities for realizing such structures are optimized and evaluated for a sample expected target FPGA technology.  ...  The paper is organized as follows. • The state of the art of PUFs as recently used unknown functions in Section 2. Other proposals of unknown functions were carefully reviewed in [6] .  ... 
doi:10.3390/cryptography4010006 fatcat:naqr2anov5hbnfm7krw7ickgni

Slender PUF Protocol: A Lightweight, Robust, and Secure Authentication by Substring Matching

Mehrdad Majzoobi, Masoud Rostami, Farinaz Koushanfar, Dan S. Wallach, Srinivas Devadas
2012 2012 IEEE Symposium on Security and Privacy Workshops  
The low overhead and practicality of the protocol are confirmed by a set of hardware implementation and evaluations. IEEE Symposium on Security and Privacy Workshops  ...  In addition, it has the great advantage of an inbuilt PUF error tolerance.  ...  (A 6-XOR arbiter PUF is currently out of reach for state-of-the-art modeling attacks.)  ... 
doi:10.1109/spw.2012.30 dblp:conf/sp/MajzoobiRKWD12 fatcat:6yp56o6xtrgcpacbaxlu3qnvmy

Robustness and Unpredictability for Double Arbiter PUFs on Silicon Data: Performance Evaluation and Modeling Accuracy

Meznah A. Alamro, Khalid T. Mursi, Yu Zhuang, Ahmad O. Aseeri, Mohammed Saeed Alkatheiri
2020 Electronics  
We generated different sets of real challenge–response pairs CRPs from three FPGA hardware boards to evaluate the performance of both DAPUF and XOR PUF designs using special-purpose evaluation metrics.  ...  This paper provides comprehensive risk analysis and performance evaluation of all proposed DAPUF designs and compares them with their counterparts from XOR PUF.  ...  The correctness of all designs is evaluated when the whole experiment on each device and for each design is iterated 32 times.  ... 
doi:10.3390/electronics9050870 fatcat:l3xc6e6h2fei5hkgenrrofaadi

Chaos-Based Physical Unclonable Functions

Krzysztof Gołofit, Piotr Wieczorek
2019 Applied Sciences  
We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits.  ...  On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences  ...  The design was successfully tested in cheap CPLDs as well as in state-of-the-art FPGAs.  ... 
doi:10.3390/app9050991 fatcat:pufdntmzxbfqrethmdkussqpf4

Hardware Security (Dagstuhl Seminar 16202)

Osnat Keren, Ilia Polian, Mark M. Tehranipoor, Marc Herbstritt
2016 Dagstuhl Reports  
This report documents the program and outcomes of Dagstuhl Seminar 16202 "Hardware Security", which was held in Schloss Dagstuhl -Leibniz Center for Informatics from May 16-20, 2016.  ...  The seminar was organized around presentations given by several participants on their current research, and ongoing work.  ...  These data are needed further to generate models of PUFs and for proper dimensioning of error correction codes.  ... 
doi:10.4230/dagrep.6.5.72 dblp:journals/dagstuhl-reports/KerenPT16 fatcat:dj5xqpsogrgtlgut3oneo6qss4

Reliable and efficient PUF-based key generation using pattern matching

Z. Paral, S. Devadas
2011 2011 IEEE International Symposium on Hardware-Oriented Security and Trust  
We describe a novel and efficient method to reliably provision and re-generate a finite and exact sequence of bits, for use with cryptographic applications, e.g., as a key, by employing one or more challengeable  ...  This means that complex error correction logic such as BCH decoders are not required.  ...  Error Correction In a typical error correction setting for PUF, during an initialization phase, the PUF is evaluated for a set of challenges. Then a syndrome is computed based on the responses.  ... 
doi:10.1109/hst.2011.5955010 dblp:conf/host/ParalD11 fatcat:pi7zbnomkrenzbw27pmw2773xm

A Survey on Physical Unclonable Function (PUF)-based Security Solutions for Internet of Things [article]

Alireza Shamsoshoara, Ashwija Korenda, Fatemeh Afghah, Sherali Zeadally
2020 arXiv   pre-print
We discuss the advantages of PUF-based key generation methods, and we present a survey of state-of-the-art techniques in this domain.  ...  This survey paper presents a review of the security challenges of emerging IoT networks and discusses some of the attacks and their countermeasures based on different domains in IoT networks.  ...  In [239] , a practical and modular design for key generation using a PUF was proposed which was evaluated on a set of FPGA devices on a ring oscillator PUF.  ... 
arXiv:1907.12525v2 fatcat:74ylrh53n5a37pbawt3fr7ivku
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