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Processor Modeling and Design Tools [chapter]

Prabhat Mishra, Nikil Dutt
2006 Industrial Information Technology  
., simulators, compilers and debuggers) to enable exploration and validation of candidate architectures.  ...  The goal is to find the best possible processor architecture for the given set of application programs under various design constraints such as cost, area, power and performance.  ...  In practice, architecture is embodied and recoverable from code by reverse engineering methods.  ... 
doi:10.1201/9781420007947.ch8 fatcat:azirpu6yajf2dkvpiiqhecdise

Issues of compatibility of processor command architectures

T R Zmyzgova, A V Solovyev, A G Rabushko, A A Medvedev, Yu V Adamenko
2020 IOP Conference Series: Earth and Environment  
The brief analysis of the components of devices and interrelations between them (different hardware features of processors, architecture of memory models and registers of peripheral devices, mechanisms  ...  The article considers the issue of creating a universal architecture of processor commands.  ...  Machine code for such an architecture should be localized and built into modules to facilitate code discovery.  ... 
doi:10.1088/1755-1315/421/4/042006 fatcat:dfvjiz5y3zc75h4m2vv4wpyeo4

Verification of Virtual Machine Architecture in a Hypervisor through Model Checking

Ram Chandra Bhushan, Dharmendra K Yadav
2020 Procedia Computer Science  
Abstract Hypervisors are used to virtualize the architecture on which it runs. These are small computer programs that are typically safetycritical, and also hard to debug.  ...  The formal verification of architecture of virtual machines along with its code written in the mCRL2 modelling language is presented.  ...  A VMM presents guest software with an abstraction of a virtual processor and allows it to execute directly on a logical processor. • Guest Software: All the virtual machines run indepently as a guest software  ... 
doi:10.1016/j.procs.2020.03.183 fatcat:cgrmpbnttjfq7hayn3kfgsxoxa

Adaptive compression of syntax trees and iterative dynamic code optimization: Two basic technologies for mobile object systems [chapter]

Michael Franz
1997 Lecture Notes in Computer Science  
Not only is this representation more than twice as dense as Java byte-codes, but it also encodes semantic information on a much higher level than linear abstract-machine representations such as p-code  ...  Since this is strictly a re-compilation of already existing code, and since it occurs completely in the background, speed is not critical, so that aggressive, albeit slow, optimization techniques can be  ...  Acknowledgment The Oberon System has turned out to be a stable foundation for projects far beyond its original scope.  ... 
doi:10.1007/3-540-62852-5_19 fatcat:mbldqf6ulzaxpd5c4qipxwzque

Architecture Description Languages [chapter]

Prabhat Mishra, Nikil Dutt
2007 Customizable Embedded Processors  
It is necessary to develop a specification language that can model complex processors at a higher level of abstraction and enable automatic analysis and generation of efficient tools and prototypes.  ...  The language should be powerful enough to capture high-level description of the processor architectures.  ...  In practice, architecture is embodied and recoverable from code by reverse engineering methods.  ... 
doi:10.1016/b978-012369526-0/50005-x fatcat:rbib63vmazbs3jpezammkjetxm

Evaluation of Stream Virtual Machine on Raw Processor

Jinwoo Suh, Richard Lethin, Stephen P. Crago, Janice O. McMahon, Dong-In Kang
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
These applications are optimized and the results are analyzed. The results show that the SVM framework is generally suitable for streaming applications on Raw processor.  ...  The authors acknowledge Morphware Forum [2] for the Streaming Virtual Machine standard upon which this implementation was performed.  ...  HLC uses machine model to generate tailored code for target architecture. The machine model describes the target machine abstractly using universal descriptions.  ... 
doi:10.1109/ipdps.2007.370403 dblp:conf/ipps/SuhLCMK07 fatcat:gviqt252pfbnhi7b22wybd5xha

Architecture description languages for programmable embedded systems

P. Mishra, N. Dutt
2005 IEE Proceedings - Computers and digital Techniques  
The ADL is used to specify programmable embedded systems, including processor, coprocessor and memory architectures.  ...  It concludes with a discussion of the relative merits and demerits of the existing ADLs and expected features of future ADLs.  ...  In practice, architecture is embodied and recoverable from code by reverse engineering methods.  ... 
doi:10.1049/ip-cdt:20045071 fatcat:sznyga75n5hk3pongpmyrmffgq

Network virtual machine (NetVM): a new architecture for efficient and portable packet processing applications

L. Degioanni, M. Baldi, D. Buffa, F. Risso, F. Stirano, G. Varenni
2005 Proceedings of the 8th International Conference on Telecommunications, 2005. ConTEL 2005.  
Similarly to a Java Virtual Machine that virtualizes a CPU, a NetVM virtualizes a network processor.  ...  This paper presents our work on designing and implementing a virtual network processor, called NetVM, which has an instruction set optimized for packet processing applications, i.e., for handling network  ...  VERA, another modular router, is a step forward for some of these issues: it has an architecture that includes a hardware abstraction, and it considers the issue of portability toward different processors  ... 
doi:10.1109/contel.2005.185843 fatcat:gfj4hyrxirgstas377m65lnzaa

Abstract machines for programming language implementation

Stephan Diehl, Pieter Hartel, Peter Sestoft
2000 Future generations computer systems  
This basic control mechanism of an abstract machine is also known as its execution loop.  ...  Common to most abstract machines are a program store and a state, usually including a stack and registers.  ...  Acknowledgements We thank David Barron, Hugh Glaser, Brian Kernighan, John Ousterhout, Guido van Rossum and Reinhard Wilhelm for their help with our research.  ... 
doi:10.1016/s0167-739x(99)00088-6 fatcat:qx6mlakihzecvlaiorgzuwdzxi


Michal ŠIPOŠ, Slavomír ŠIMOŇÁK
2017 Acta Electrotechnica et Informatica  
This paper presents the RASP (Random Access Stored Program) abstract machine emulator implemented as a plugin for emuStudio -extendable platform for computer architectures emulation.  ...  It consists of three submodules -the CPU emulator (the core of the plugin), main memory for storing RASP machine's program and data and compiler of RASP assembly language.  ...  Another fact that can make the process of reverse engineering even more difficult is code obfuscation [8] , which is a way of making either source code or machine code difficult to read and understand  ... 
doi:10.15546/aeei-2017-0024 fatcat:bhxrdriphjerbccyrgy7ga6to4

A methodology for accurate performance evaluation in architecture exploration

George Hadjiyiannis, Pietro Russo, Srinivas Devadas
1999 Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99  
We present a system that automatically generates a cycle-accurate and bit-true Instruction Level Simulator (ILS) and a hardware implementation model given a description of a target processor.  ...  Our system uses the ISDL machine description language to support the automatic generation of the ILS and the hardware synthesis model, as well as other related tools.  ...  In this approach, the application code is analyzed, and an initial target architecture is generated and described in a machine description language.  ... 
doi:10.1145/309847.310100 dblp:conf/dac/HadjiyiannisRD99 fatcat:dfrlvygqsbanpjqyq7t7bhhfqm

Rethinking the design of virtual machine monitors

A. Whitaker, R.S. Cox, M. Shaw, S.D. Gribble
2005 Computer  
Over the past several years, our research group has developed the Denali VMM (denali.cs., working from the premise that it is both possible and useful to consider a virtual machine abstraction  ...  However, traditional VMMs suffer from poor scalability and extensibility.  ...  An alternative to modifying source code is to reverse engineer a black-box VMM such as VMware.  ... 
doi:10.1109/mc.2005.169 fatcat:7gahtbnqzbcezlxdhplbqb2vse

Theory of Multi Core Hypervisor Verification [chapter]

Ernie Cohen, Wolfgang Paul, Sabine Schmaltz
2013 Lecture Notes in Computer Science  
For example, the kernel code itself has to set up low-level facilities such as its call stack and virtual memory map, and must continue to use memory in a way that justifies the memory model assumed by  ...  However, there is a significant gap between code verification of a kernel (such as a hypervisor) and a proof of correctness of a real system running the code.  ...  86, which is simply MIPS processor cores extended with x86-64 like architecture features (in particular, memory system and interrupt controllers), ii) we reverse engineer the machine in a plausibly efficient  ... 
doi:10.1007/978-3-642-35843-2_1 fatcat:fe62ercjczcxrkl7te7ifyc56e

Design of a Retargetable Decompiler for a Static Platform-Independent Malware Analysis [chapter]

Lukáš Ďurfina, Jakub Křoustek, Petr Zemek, Dušan Kolář, Tomáš Hruška, Karel Masařík, Alexander Meduna
2011 Communications in Computer and Information Science  
In this case, the code viewing and walking is done by several reverse-engineering tools like disassemblers or decompilers [4, 5] . The reverse translation of malware gives the analyst an opportunity  ...  In dynamic analysis, we inspect a run-time malware behavior by its monitoring (e.g. monitoring of WinAPI calls [1]) and we track changes of the system and network (e.g. registry modification, installation  ...  With its help, it will be possible to inspect malware code on a much more abstract and unified form of representation, while preserving the functional equivalence of the code.  ... 
doi:10.1007/978-3-642-23141-4_8 fatcat:4yuspddlf5fnzbzuwxzoufchkq

Efficient High-Level Power Estimation for Multi-standard Wireless Systems

Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
2008 2008 IEEE Computer Society Annual Symposium on VLSI  
The simulator has been applied to the SystemC modules of a WiMAX receiver based on ARM processor, reconfigurable FFT and Viterbi, and AMBA bus.  ...  It allows efficient power estimation of reconfigurable cores by state based power modelling, which leads to a viable solution for early power aware design of multistandard Wireless systems.  ...  Here, we use two reverse processors B1 and B2 in parallel with one forward processor FP.  ... 
doi:10.1109/isvlsi.2008.56 dblp:conf/isvlsi/AhmadiniaAA08a fatcat:ty5ykroefjbvpbbrcgfbwgemcy
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