Filters








22 Hits in 4.2 sec

Revealing DRAM Operating GuardBands through Workload-Aware Error Predictive Modeling

Lev Mukhanov, Konstantinos Tovletoglou, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
2020 IEEE transactions on computers  
We use a Machine Learning (ML) method to build a workload-aware DRAM error behavior model based on the program features which we extract from real workloads during our DRAM error characterization campaign  ...  The main idea behind the proposed approach is that DRAM error behavior is workload-dependent and can be predicted based on particular program inherent features.  ...  ACKNOWLEDGMENTS This work was funded by the H2020 Framework Program of the European Union through the UniServer Project (Grant Agreement 688540, http://www.uniserver2020.eu) and OpreComp project (Grant  ... 
doi:10.1109/tc.2020.3033627 fatcat:peobjdxer5g3do4nobwm452cz4

Understanding Reduced-Voltage Operation in Modern DRAM Devices

Kevin K. Chang, Onur Mutlu, A. Giray Yağlıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan
2017 Proceedings of the ACM on Measurement and Analysis of Computing Systems  
We discover that these errors can be avoided by increasing the latency of three major DRAM operations (activation, restoration, and precharge).  ...  The key idea of Voltron is to use a performance model to determine by how much we can reduce the supply voltage without introducing errors and without exceeding a user-specified threshold for performance  ...  Vendors choose a conservatively high supply voltage, to provide a guardband that allows DRAM chips with the worst-case process variation to operate without errors under the worst-case operating conditions  ... 
doi:10.1145/3084447 dblp:journals/pomacs/ChangYGACKLOHM17 fatcat:oaonzbkwpjhj5jabnmklgdgmn4

An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits

Georgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikos Bellas, Spyros Lalis (+14 others)
2018 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
Low overhead schemes are employed to monitor and predict the hardware behavior and report it to the system software.  ...  at new extended operating points.  ...  Using the information provided by the HealthLog and StressLog, the Predictor develops probability failure models and tries to predict the hardware behavior under any operating point and eventually helping  ... 
doi:10.23919/date.2018.8342175 dblp:conf/date/KarakonstantisT18 fatcat:q7nxvds5mnhn7nv2pouokoayu4

Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software

Abbas Rahimi, Luca Benini, Rajesh K. Gupta
2016 Proceedings of the IEEE  
We consider methods to predict and prevent, detect and correct, and finally conditions under which such errors can be accepted; we also consider their implications on cost, performance and quality.  ...  | Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in modern microelectronic manufacturing processes with geometries in nanometer scales  ...  It aims to reduce the very frequent refresh rate of DRAMs by revealing the statistical characteristics of the retention time, in addition to exploiting the error resilient nature applications. 3) Software  ... 
doi:10.1109/jproc.2016.2518864 fatcat:sxrsu3excbdg5p7sk4iczz262y

Understanding and Improving the Latency of DRAM-Based Memory Systems [article]

Kevin K. Chang
2017 arXiv   pre-print
The key conclusion of this dissertation is that augmenting DRAM architecture with simple and low-cost features, and developing a better understanding of manufactured DRAM chips together lead to significant  ...  Therefore, long DRAM latency continues to be a critical performance bottleneck in modern systems.  ...  We show that enhancing Voltron by adding awareness of the spatial locality of errors can further mitigate the latency penalty due to reduced voltage, even with the conservative bank error locality model  ... 
arXiv:1712.08304v1 fatcat:6y2nr2eowvb5fhr7km7azmkioe

EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures

Renji Thomas, Naser Sedaghati, Radu Teodorescu
2016 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
A distributed power delivery model at functional unit granularity was developed and used to simulate supply voltage behavior in a GPU system.  ...  We observe that resonance noise can lead to very large voltage droops and protecting against these droops by using voltage guardbands is costly and inefficient.  ...  The framework includes a resonance-aware warp-level scheduler, designed to anticipate workload activity patterns that could lead to voltage noise.  ... 
doi:10.1109/ispass.2016.7482076 dblp:conf/ispass/ThomasST16 fatcat:hkc7wd67avhh5k4c3dd2u3erti

Architectural Techniques for Improving NAND Flash Memory Reliability [article]

Yixin Luo
2018 arXiv   pre-print
We analyze flash error characteristics and workload behavior through experimental characterization, and design new flash controller algorithms that use the insights gained from our analysis to improve  ...  . (3) We identify three new error characteristics in 3D NAND through a comprehensive experimental characterization of real 3D NAND chips, and propose four new techniques that mitigate these new errors  ...  The techniques we propose in Chapter 7 exploits workload write-intensity awareness and environment temperature awareness to mitigate retention errors in 3D NAND.  ... 
arXiv:1808.04016v1 fatcat:fotned4yajc2xmaoezwjdrgypu

IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors [article]

Jawad Haj-Yahya, Jeremie S. Kim, A. Giray Yaglikci, Ivan Puddu, Lois Orosa, Juan Gómez Luna, Mohammed Alser, Onur Mutlu
2021 arXiv   pre-print
To operate efficiently across a wide range of workloads with varying power requirements, a modern processor applies different current management mechanisms, which briefly throttle instruction execution  ...  We propose practical and effective mitigations to each covert channel in IChannels by leveraging the insights we gain through a rigorous characterization of real systems.  ...  Such a threat model consists of two malicious user-level attacker applications, sender and receiver, that cannot communicate legitimately through overt channels.  ... 
arXiv:2106.05050v2 fatcat:4z5c5vvbzbbbzgbpry6gldycr4

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Jeren Samandari-Rad, Richard Hughey
2016 IEEE Access  
In this paper, we extend our previously proposed hybrid analyticalempirical model for minimizing and predicting the delay and delay variability of SRAMs, VAR-TX, to a new enhanced version, exVAR-TX, to  ...  minimize and predict the power/energy and power/energy variability of a 16-nm 6T-SRAM under the influence of the three major types of variations: Fabrication, Operation, and Implementation.  ...  Proposing exVAR-TX: our newly enhanced statistical timing analysis based, hybrid analytical-empirical model that helps predict the variation of leakage and power due to process, operational, and aging  ... 
doi:10.1109/access.2016.2521385 fatcat:vowwzjai7jhg3iezcclnpdph3e

Rubik

Harshad Kasture, Davide B. Bartolini, Nathan Beckmann, Daniel Sanchez
2015 Proceedings of the 48th International Symposium on Microarchitecture - MICRO-48  
We propose Rubik, a fine-grain DVFS scheme for latency-critical workloads. Rubik copes with variability through a novel, general, and efficient statistical performance model.  ...  This model allows Rubik to adjust frequencies at sub-millisecond granularity to save power while meeting the target tail latency.  ...  On 20,000 25 ms samples of SPEC CPU2006 mixes at different frequencies, the model has 5.1% mean, and 11% worst-case absolute power error; core, uncore, and DRAM have lower errors (1.5% mean, 4% worst-case  ... 
doi:10.1145/2830772.2830797 dblp:conf/micro/KastureBBS15 fatcat:doivdbbc7rdkhfbixin5gpghbq

Reliability Modeling and Mitigation for Embedded Memories

Innocent Okwudili Agbo, Mottaqiallah Taouil, Said Hamdioui
2019 2019 IEEE International Test Conference (ITC)  
and RD model), different technology nodes (i.e., 90, 65, 45, 32, 22, and 16 nm), and different workloads.  ...  This reveals that there must be a tradeoff between performance and reliability.  ...  This is known as a soft error; and the occurrence rate of this error is known as soft error rate [59] .  ... 
doi:10.1109/itc44170.2019.9000175 dblp:conf/itc/AgboTH19 fatcat:kok7bod22rd7bkxa4aizas65de

Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated Architectures

Theonitsa Alexoudi, Nikolaos Terzenidis, Stelios Pitris, Miltiadis Moralis-Pegios, Pavlos Maniotis, Christos Vagionas, Charoula Mitsolidou, George Mourgias-Alexandris, George T. Kanellos, Amalia Miliou, Konstantinos Vyrsokinos, Nikos Pleros
2019 Journal of Lightwave Technology  
Alexoudi acknowledges support from the IKY scholarships program that is co-financed by the European Union (European Social Fund -ESF) and Greek national funds through the action entitled "Reinforcement  ...  of Postdoctoral Researchers", in the framework of the Operational Programme "Human Resources Development Program, Education and Lifelong Learning" of the National Strategic Reference Framework (NSRF)  ...  The modelled DC system featured node-to-switch and nodeto-AWGR channel datarate of 10 Gb/s, along with fixed size packet-length of 72 bytes, comprising 8-bytes for header, synchronization and guardband  ... 
doi:10.1109/jlt.2018.2875995 fatcat:gxlflc7gfjfqrd7f3efmoiq3uy

Design for Reliability and Low Power in Emerging Technologies

Sami Alsalamin
2021
Hence, applying input compression through quantization can mitigate aging-induced timing errors and eliminate the required guardband, which is presented here.  ...  In practice, power/energy management always consists of two parts: (1) predicting future workload characteristics and (2) selecting (V/f) pairs based on the prediction.  ...  Precision Scaling Modeling through NN Quantization Precision scaling is a widely-used technique to reduce the power of circuits.  ... 
doi:10.5445/ir/1000137950 fatcat:adcjcweifreytfrfmlt6hbd3vy

Understanding and Improving the Latency of DRAM-Based Memory Systems

Kevin K. Chang
2018
First, while bulk data movement is a key operation in many applications and operating systems, contemporary systems perform this movement inefficiently, by transferring data from DRAM to the processor,  ...  and then back to DRAM, across a narrow o -chip channel.  ...  We show that enhancing Voltron by adding awareness of the spatial locality of errors can further mitigate the latency penalty due to reduced voltage, even with the conservative bank error locality model  ... 
doi:10.1184/r1/6724127.v1 fatcat:gjvlf6dju5eg3kjz6nfjn3shie

Design space exploration in near-data co-processors for general-purpose acceleration, in high-performance and low-power processing environments [article]

Αθανάσιος Σ. Τζιουβάρας, University Of Thessaly, Γεώργιος Σταμούλης
2021
In contrast to the traditional model, the BTWC paradigm attempts to relax any critical path restrictions through TS, by scaling up and down the processor voltage or clock frequency, allowing timing errors  ...  Since we are a priory aware of such constraints we do not deploy any error detection or error correction mechanisms and thus, the hardware implementation costs are significantly reduced. • We co-design  ... 
doi:10.26253/heal.uth.12760 fatcat:c5tcx5afvjc67f3z4rkxpofuyy
« Previous Showing results 1 — 15 out of 22 results