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Retiming synchronous circuitry

Charles E. Leiserson, James B. Saxe
1991 Algorithmica  
We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria.  ...  This result yields a polynomial-time optimal solution to the problem of pipelining combinational circuitry with minimum register cost.  ...  Flavio was a contributor to the first general algorithm for retiming circuits, which appeared in [13] and [19] .  ... 
doi:10.1007/bf01759032 fatcat:26vqhli7zjbqnnogw7olu637de

Retiming synchronous circuitry with imprecise delays

I. Karkowski, R. H. J. M. Otten
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
It is shown that the computational complexity is the same as for retiming with exact circuit delays.  ...  In this paper possibilistic programming is proposed for handling the retiming problem where delays are modelled as (triangular) possibilistic numbers.  ...  To solve problem of eq. 2 any MOLP technique can be used (e.g. utility theory, goal programming, fuzzy programming or interactive programming). 2 Retiming synchronous circuitry with imprecise propagation  ... 
doi:10.1145/217474.217549 dblp:conf/dac/KarkowskiO95 fatcat:i2jdaqpmbrhgval6g7fvwf55la

Retiming Synchronous Circuitry with Imprecise Delays

I. Karkowski
1995 Proceedings - Design Automation Conference  
It is shown that the computational complexity is the same as for retiming with exact circuit delays.  ...  In this paper possibilistic programming is proposed for handling the retiming problem where delays are modelled as (triangular) possibilistic numbers.  ...  To solve problem of eq. 2 any MOLP technique can be used (e.g. utility theory, goal programming, fuzzy programming or interactive programming). 2 Retiming synchronous circuitry with imprecise propagation  ... 
doi:10.1109/dac.1995.249967 fatcat:zpjeidb4mzdorhwofxns6z5jui

On Some Transformation Invariants Under Retiming and Resynthesis [chapter]

Jie-Hong R. Jiang
2005 Lecture Notes in Computer Science  
(Doing so admits a more systematic treatment of retiming synchronous hardware systems because retiming explicit-reset registers needs special attention to maintain equivalent initial states.)  ...  Transformations using retiming and resynthesis operations are the most important and practical (if not the only) techniques used in optimizing synchronous hardware systems.  ...  Introduction Retiming [7, 8] is an elementary yet effective technique in optimizing synchronous hardware systems.  ... 
doi:10.1007/978-3-540-31980-1_27 fatcat:kwdjusdpvbcopapejo5gsu74re

Performance driven resynthesis by exploiting retiming-induced state register equivalence

Priyank Kalla, Maciej J. Ciesielski
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
The results demonstrate a favourable performance/area trade-off when compared with optimally retimed circuits.  ...  This paper presents a retiming and resynthesis technique for cycle-time minimization of sequential circuits circuits with feedbacks (finite state machines).  ...  If, however, explicit reset circuitry is not available, then we need to compute a synchronizing sequence to drive the retimed circuit to its corresponding equivalent initial state.  ... 
doi:10.1145/307418.307579 fatcat:bir22zdvnfafneqc4v3jlajesi

Page 425 of Mathematical Reviews Vol. , Issue 95a [page]

1995 Mathematical Reviews  
We give tight bounds on the minimum clock period that can be achieved by retiming a synchronous circuit.  ...  Finally, we give an O(Elgd,,x) algorithm for minimum clock-period pipelining of combinational circuitry.”  ... 

Different approaches of high speed data transmission standards

M. Ehlert
2005 Advances in Radio Science  
The main focus lies on the approaches used for physical signaling, line coding and information synchronization in serial and serialparallel systems.  ...  While 8B10B encoding and decoding takes considerably more circuitry to implement, TMDS is more difficult to deal with for the bit synchronization at the receiver.  ...  As a result, the amount off circuitry on the upstream side is greatly reduced (see Fig. 11 ). Common to all the bit synchronization techniques is the need for transitions in the input signal.  ... 
doi:10.5194/ars-2-187-2004 fatcat:47kwo5tgerfcxb6iq7w3cjudha

Probabilistic Evaluation of Solutions in Variability-Driven Optimization

Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Transformations using retiming and resynthesis operations are the most important and practical (if not the only) techniques used in optimizing synchronous hardware systems.  ...  As a result, we advocate a conservative design methodology for the optimization of synchronous hardware systems to ameliorate verifiability.  ...  For registers with explicit reset, their initial values are determined by some reset circuitry when the system is powered up.  ... 
doi:10.1109/tcad.2006.882529 fatcat:uiqudvxhszfbbowfe4kcwn3rtu

Probabilistic evaluation of solutions in variability-driven optimization

Azadeh Davoodi, Ankur Srivastava
2006 Proceedings of the 2006 international symposium on Physical design - ISPD '06  
Transformations using retiming and resynthesis operations are the most important and practical (if not the only) techniques used in optimizing synchronous hardware systems.  ...  As a result, we advocate a conservative design methodology for the optimization of synchronous hardware systems to ameliorate verifiability.  ...  For registers with explicit reset, their initial values are determined by some reset circuitry when the system is powered up.  ... 
doi:10.1145/1123008.1123013 dblp:conf/ispd/DavoodiS06 fatcat:w6ntpmacejcojnyw3jux73ohzm

Retiming and Resynthesis: A Complexity Perspective

Jie-Hong R. Jiang, Robert K. Brayton
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Transformations using retiming and resynthesis operations are the most important and practical (if not the only) techniques used in optimizing synchronous hardware systems.  ...  As a result, we advocate a conservative design methodology for the optimization of synchronous hardware systems to ameliorate verifiability.  ...  For registers with explicit reset, their initial values are determined by some reset circuitry when the system is powered up.  ... 
doi:10.1109/tcad.2006.882520 fatcat:d7php547kfdvtgdsd3q6yjveum

Constrained clock shifting for field programmable gate arrays

Deshanand P. Singh, Stephen D. Brown
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
Figure 4 : Phase Shifting Circuitry.  ...  SYNCHRONOUS OPERATION WITH CLOCK SKEW In this section, we briefly review the fundamentals of synchronous circuits operating in the presence of clock skew.  ... 
doi:10.1145/503048.503067 dblp:conf/fpga/SinghB02a fatcat:v3tqunqn3rccnpqpdcudkonn3m

Retiming and resynthesis: optimizing sequential networks with combinational techniques

S. Malik, E.M. Sentovich, R.K. Brayton, A. Sangiovanni-Vincentelli
1991 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
the registers using existing logic minimization techniques, and replacing the registers throughout the network using retiming algorithms.  ...  We propose a technique for optimizing a sequential network by moving the registers to the boundary of the network using an extension of retiming [SI, 191, resynthesizing the combinational logic between  ...  is synchronous.  ... 
doi:10.1109/43.62793 fatcat:lzdxofsvvff2nehnkiyyelk3zq

Area efficient pipelined pseudo-exhaustive testing with retiming

Huoy-Yu Liou, Ting-Ting Y. Lin
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
Circuit partitioning with retiming is used to convert designs for PPET. Experimental results show that this approach exhibits an average of 20% area reduction over non-retimed testable circuits.  ...  Retiming Principles Retiming is an operation on synchronous circuits which deletes or adds registers to a circuit to meet certain performance constraint(s) [1] .  ...  Let be a retiming on a synchronous circuit, . If , is a path in , let represent the number of registers in . Thus we have for each path , . (1) Corollary 2.  ... 
doi:10.1145/240518.240569 dblp:conf/dac/LiouLC96 fatcat:djq6fagcnzfc3exjv4drjrfwie

A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming

S. Mendel, C. Vogel, N. Da Dalt
2009 IEEE Transactions on Circuits and Systems - II - Express Briefs  
State-of-the-art phase-domain all-digital phaselocked loops (ADPLLs) require a retimed reference clock to synchronize the digitally controlled oscillator (DCO) output frequency and the reference clock  ...  Behavioral simulations verify the spur analysis and emphasize the improved behavior of the proposed synchronous reference architecture.  ...  uses a retimed reference clock CKR to synchronize the reference phase ϕ r [m] and the variable phase ϕ v [i], where the signal ε[m] compensates for the retiming error [2]- REF clock and the CKV clock  ... 
doi:10.1109/tcsii.2009.2034079 fatcat:y6yqq4vqknbkxe3oztgcd3n36a

Editorial

Vishwani D. Agrawal
2013 Journal of electronic testing  
Saxe, "Retiming Synchronous Circuitry," Algorithmica, volume 6, pp. 1991) .  ...  The next paper presents a method for testing two-D-flipflop synchronizers of an asynchronous first-in-first-out (FIFO) interface.  ... 
doi:10.1007/s10836-013-5353-4 fatcat:fa5nzr26rbgizldvoxcjvjkabi
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