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Scaling the capacity of memory systems; evolution and key approaches

Kyriakos Paraskevas, Andrew Attwood, Mikel Lujan, John Goodacre
2019 Proceedings of the International Symposium on Memory Systems - MEMSYS '19  
providing, and therefore the requirement of delivering a scalable memory capacity still poses a real challenge for system architects.  ...  interconnects and abstractions via system hypervisors, where each approach allows a more efficient way of memory resource allocation and usage between different nodes in a machine cluster.  ...  A stepper machine first makes a number of passes around the wafer, successively projecting the image of each die layer through a photomask ,or reticle, and then, after several chemical procedures, each  ... 
doi:10.1145/3357526.3357555 dblp:conf/memsys/ParaskevasALG19 fatcat:qlsuo7csujg3rhbwf3efqljhta

A Review of Spiking Neuromorphic Hardware Communication Systems

Aaron R. Young, Mark E. Dean, James S. Plank, Garrett S. Rose
2019 IEEE Access  
Not only is this tube a literal bottleneck for the data traffic of a problem, but, more importantly, it is an intellectual bottleneck that has kept us tied to wordat-a-time thinking instead of encouraging  ...  Additional topics, such as the use of asynchronous circuits, robustness in communication, connection with a host machine, and network synchronization are also covered.  ...  Eight high input count analog neural networks (HICANNs) are grouped into one reticle. The reticle is then connected to one DNC. Four DNCs are connected to an FPGA-AER board.  ... 
doi:10.1109/access.2019.2941772 fatcat:dugxbgbftrakpdi6t23337faby

D5.1: Market and Technology Watch Report Year1

Nico Sanna, Aris Sotiropoulos
2018 Zenodo  
Core technologies for HPC system processors mostly rely on Intel Sky/Cascade/Ice Lake silicon development for present and near future X86 systems.  ...  This document is the first deliverable of PRACE-5IP Work Package 5 "Task 5.1 - Technology and market watch" and corresponds to a periodic annual update on technology and market trends.  ...  Notable mentions are new Intel "Skylake" based virtual machines, now with 25 Gbit Ethernet connectivity.  ... 
doi:10.5281/zenodo.6805965 fatcat:656msfaojzhfznp4kwta7jkyyy

Logic Synthesis [chapter]

2017 Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology  
ACKNOWLEDGMENT e authors thank Vladimir Yutsis for his helpful feedback on Section 1.5.2.  ...  Putnam, A computing procedure for quanti�cation theory, J. Assoc. Comput. Mach., 7, 201-215, 1960. 19. M. Davis, G. Logemann, and D. Loveland, A machine program for theorem proving, Commn.  ...  PARALLEL AND DISTRIBUTED COMPUTING FOR EDA EDA vendors are migrating tools to work in a distributed manner with a controller on one machine distributing task to workers on other machines to perform in  ... 
doi:10.1201/9781315215112-13 fatcat:me52zpnxyfcczh3choo2p4zulm

D5.2: Market and Technology Watch Report Year 2

Ioannis Liabotis
2017 Zenodo  
This deliverable is the second one of PRACE-4IP Work Package 5 Task 1, it corresponds to a periodic annual update on technology and market trends.  ...  The PRACE-4IP Work Package 5 (WP5), "Best Practices for HPC Systems Commissioning", has three objectives: Procurement independent vendor relations and market watch (Task 1) Best practices for energy-efficient  ...  In IaaS cloud capacity is offered using virtualization technology. On each node a hypervisor runs multiple virtual machines (VMs, or "instances") on virtual operating platforms.  ... 
doi:10.5281/zenodo.6801691 fatcat:jfhjlhwi5fbanmb7xml7rfrhpu

Device Packaging

2021 Advancing Microelectronics Magazine  
KG, Geislingen, Germany and Schmoll Maschinen GmbH, Rödermark, Germany for their valuable input within the project.  ...  Acknowledgements The authors would like to thank the German Ministry of Education and Research for the financial support of project PEKOS (FKZ 16ES0718K).  ...  Chip placement was performed with a die bond machine on 303 mm x 227 mm panel size and an assembly machine for larger panels.  ... 
doi:10.4071/2380-7016-48.1.1 fatcat:ck7dh4qc3zdjfil37agsvyy65m

Operating Accelerated Neuromorphic Hardware - A Scalable and Sustainable Approach

Christian Paul Mauch
Finally, a monitoring infrastructure vital for system commissioning and experiment reproducibility is established.  ...  This thesis addresses these in two ways: First a multi-layered software architecture developed for the second-generation BrainScaleS neuromorphic systems is presented.  ...  My desk buddy Philipp for providing a very short feedback loop. Joscha for starting the visionary brewing culture.  ... 
doi:10.11588/heidok.00030979 fatcat:q3gdxru2i5aava3o2vpq7bfbzq


2021 2021 IEEE International 3D Systems Integration Conference (3DIC)  
To meet the increasing demand for large-scale data analysis, data centers need low latency and significant memory bandwidth, combined with lower power consumption.  ...  Machine learning, deep learning, autonomous driving, and other artificial intelligence applications are driving the performance requirements of next generation computing hardware.  ...  He has served on the Fellows' committee for EDS and IEEE. He is also a member of the APS.  ... 
doi:10.1109/3dic52383.2021.9687605 fatcat:m27oybj3brhilb2m6bkb76k5ia

Technical Design Report for the PANDA Barrel DIRC Detector [article]

PANDA Collaboration
2017 arXiv   pre-print
This documents describes the technical design and the expected performance of the Barrel DIRC detector for the PANDA experiment.  ...  The Barrel DIRC will provide hadronic charged particle identification in the polar angle range of 22^∘ to 140^∘ for particle momenta between 0.5 GeV/c and 3.5 GeV/c.  ...  coordinate mea- suring machine.  ... 
arXiv:1710.00684v1 fatcat:6ik3sbcsqvd23jcz5xst3z2ziq

Technical Design Report for the PANDA Barrel DIRC Detector

J Schwiening
2018 Journal of Physics G: Nuclear and Particle Physics  
of registered names, trademarks, etc in this publication does not imply, even in the absence of specific statement, that such names are exempt from the relevant laws and regulations and therefore free for  ...  We thank GSI and CERN staff for the opportunity to use the beam facilities and for their on-site support. ORCID iDs J Schwiening  ...  Acknowledgments This work was supported by the Bundesministerium für Bildung und Forschung (BMBF), HGS-HIRe, HIC for FAIR, the European Community FP6 FAIR Design Study: DIRAC secondary-Beams, contract  ... 
doi:10.1088/1361-6471/aade3d fatcat:blddnjwmkjdnpf5cs6aevsq7ai

Next Frontiers in Particle Physics Detectors: INSTR2020 Summary and a Look into the Future [article]

Maxim Titov
2020 arXiv   pre-print
for Colliding Beam Physics" (INSTR-20), held at BINP Novosibirsk, Russia, from 24 to 28 February, 2020.  ...  The timescales spanned by future projects in particle physics, ranging from few years to many decades, constitute a challenge in itself, in addition to the complexity and diversity of the required accelerator  ...  Acknowledgments In preparing for this talk I benefitted from conversations with and material from: Phil Allport, Ties Behnke, Jim Brau, Paul Colas, Silvia Dalla Torre, Simon Eidelman, Eckhard Elsen, Henry  ... 
arXiv:2006.08239v3 fatcat:relsjjfc5vfankrg4opxg3ovea

Limitations and challenges of computer-aided design technology for CMOS VLSI

R.E. Bryant, Kwang-Ting Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J.M. Rabaey, A. Sangiovanni-Vincentelli
2001 Proceedings of the IEEE  
For example, there is a need to design correct and testable chips in a very short time frame and for these chips to meet a competitive requirement.  ...  A second limitation is that the effectiveness of the design process is determined by its context-the design methodologies and flows we employ, and the designs that we essay-perhaps more than by its component  ...  Fig. 3 . 3 Basic RTL-to-mask flow for VLSI design. Fig. 4 . 4 Wirelength as a function of fanout for a modern design (source: Wilsin Gosti).  ... 
doi:10.1109/5.915378 fatcat:jocv62sorfbnjp53u7b76j4mdi

Electronic warfare systems

A.E. Spezio
2002 IEEE transactions on microwave theory and techniques  
In a military application, EW provides the means to counter, in all battle phases, hostile actions that involve the electromagnetic (EM) spectrum-from the beginning when enemy forces are mobilized for  ...  EM spectrum CMs to threat systems can be selectively applied on a time-and/or frequency-multiplexed basis so that host force use of the EM spectrum is uninhibited.  ...  array (FPGA).  ... 
doi:10.1109/22.989948 fatcat:4tg7ub3dordavnqseqmv3smfuy

Reminiscences of the VLSI Revolution: How a Series of Failures Triggered a Paradigm Shift in Digital Design

Lynn Conway
2012 IEEE Solid-State Circuits Magazine  
Innovations in science and engineering have excited me for a lifetime, as they have for many friends and colleagues.  ...  The child who once dreamed of "making a difference," indeed made a difference after all. And with that, I'd like to inspire YOU to imagine how you too can positively impact our world.  ...  Acknowledgements Many people named in these reflections played vital roles in the VLSI design revolution; it was a thrill to join them on this great adventure.  ... 
doi:10.1109/mssc.2012.2215752 fatcat:mtnxjbobr5ckdozgrllnffxbri

Infrastructure for Detector Research and Development towards the International Linear Collider [article]

J. Aguilar, P. Ambalathankandy, T. Fiutowski, M. Idzik, Sz. Kulis, D. Przyborowski, K. Swientek, A. Bamberger, M. Köhli, M. Lupberger, U. Renz, M. Schumacher, Andreas Zwerger (+256 others)
2012 arXiv   pre-print
The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider.  ...  The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.  ...  A flatness of below 1 mm of machined plates would increase the costs by a factor of 2 to 3.  ... 
arXiv:1201.4657v1 fatcat:6gmm6jlirrhq3ar6tggd5ht6yq
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